175 lines
7.4 KiB
Lua
175 lines
7.4 KiB
Lua
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---
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--- DIGCTL
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---
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STMP.clkctrl = {}
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local h = HELP:get_topic("STMP"):create_topic("clkctrl")
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h:add("The STMP.clkctrl table handles the clkctrl device for all STMPs.")
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local hh = h:create_topic("list_all")
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hh:add("The STMP.clkctrl.list_all() function returns the list of all clocks names.")
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local hh = h:create_topic("is_enabled")
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hh:add("The STMP.clkctrl.is_enabled(clk) function returns the state of the clock gate or true is there is none.")
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hh:add("Note that some clock is disabled though other means than a clock gate (divider gate).")
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local hh = h:create_topic("is_enabled")
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hh:add("The STMP.clkctrl.is_enabled(clk) function returns the state of the clock gate or true is there is none.")
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hh:add("Note that some clock is disabled though other means than a clock gate (divider gate).")
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local hh = h:create_topic("get_div")
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hh:add("The STMP.clkctrl.get_div(clk) function returns the integer divider of the clock or 1 if there is none.")
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local hh = h:create_topic("get_frac_div")
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hh:add("The STMP.clkctrl.get_frac_div(clk) function returns the fractional divider of the clock gate or 1 is there is none.")
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hh:add("Note that the effect of a fractional divider might depend on other fields or on the clock itself.")
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local hh = h:create_topic("get_bypass")
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hh:add("The STMP.clkctrl.get_bypass(clk) function returns the state of the PLL bypass of the clock or false if there is none.")
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local hh = h:create_topic("get_freq")
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hh:add("The STMP.clkctrl.get_frac(clk) function returns the frequency of the clock in HZ, or 0 if it is disabled.")
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function STMP.clkctrl.list_all()
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local list = {"clk_pll", "clk_xtal", "clk_io", "clk_cpu", "clk_hbus", "clk_ssp",
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"clk_emi", "clk_xbus", "clk_filt", "clk_dri", "clk_pwm", "clk_timrot",
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"clk_uart"}
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if hwstub.dev.stmp.chipid >= 0x3700 then
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table.insert(list, "clk_pix")
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end
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return list
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end
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function STMP.clkctrl.is_enabled(clk)
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if clk == "clk_pll" then return HW.CLKCTRL.PLLCTRL0.POWER.read() == 1
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elseif clk == "clk_pix" then return HW.CLKCTRL.PIX.CLKGATE.read() == 0
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elseif clk == "clk_ssp" then return HW.CLKCTRL.SSP.CLKGATE.read() == 0
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elseif clk == "clk_dri" then return HW.CLKCTRL.XTAL.DRI_CLK24M_GATE.read() == 0
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elseif clk == "clk_pwm" then return HW.CLKCTRL.XTAL.PWM_CLK24M_GATE.read() == 0
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elseif clk == "clk_uart" then return HW.CLKCTRL.XTAL.UART_CLK24M_GATE.read() == 0
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elseif clk == "clk_filt" then return HW.CLKCTRL.XTAL.FILT_CLK24M_GATE.read() == 0
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elseif clk == "clk_timrot" then return HW.CLKCTRL.XTAL.TIMROT_CLK24M_GATE.read() == 0
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else return true end
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end
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function STMP.clkctrl.get_div(clk)
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if hwstub.dev.stmp.chipid >= 0x3700 then
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if clk == "clk_pix" then return HW.CLKCTRL.PIX.DIV.read()
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elseif clk == "clk_cpu" then return HW.CLKCTRL.CPU.DIV_CPU.read()
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elseif clk == "clk_emi" then return HW.CLKCTRL.EMI.DIV_EMI.read() end
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else
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if clk == "clk_cpu" then return HW.CLKCTRL.CPU.DIV.read()
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elseif clk == "clk_emi" then return HW.CLKCTRL.EMI.DIV.read() end
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end
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if clk == "clk_ssp" then return HW.CLKCTRL.SSP.DIV.read()
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elseif clk == "clk_hbus" then return HW.CLKCTRL.HBUS.DIV.read()
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elseif clk == "clk_xbus" then return HW.CLKCTRL.XBUS.read()
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else return 0 end
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end
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function STMP.clkctrl.get_frac_div(clk)
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local name = nil
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if hwstub.dev.stmp.chipid >= 0x3700 and clk == "clk_pix" then name = "PIX"
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elseif clk == "clk_io" then name = "IO"
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elseif clk == "clk_cpu" then name = "CPU"
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elseif clk == "clk_emi" then name = "EMI"
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else return 0 end
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if name == nil then return 0 end
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if HW.CLKCTRL.FRAC["CLKGATE" .. name].read() == 1 then return 0
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else return HW.CLKCTRL.FRAC[name .. "FRAC"].read() end
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end
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function STMP.clkctrl.get_bypass(clk)
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if hwstub.dev.stmp.chipid >= 0x3700 and clk == "clk_pix" then return HW.CLKCTRL.CLKSEQ.BYPASS_PIX.read() == 1
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elseif clk == "clk_ssp" then return HW.CLKCTRL.CLKSEQ.BYPASS_SSP.read() == 1
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elseif clk == "clk_cpu" then return HW.CLKCTRL.CLKSEQ.BYPASS_CPU.read() == 1
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elseif clk == "clk_emi" then return HW.CLKCTRL.CLKSEQ.BYPASS_EMI.read() == 1
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else return false end
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end
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function STMP.clkctrl.get_freq(clk)
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if clk == "clk_pll" then
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return STMP.clkctrl.is_enabled(clk) and 480000000 or 0
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elseif clk == "clk_xtal" then return 24000000
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elseif clk == "clk_cpu" then
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if hwstub.dev.stmp.chipid >= 0x3700 then
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if STMP.clkctrl.get_bypass(clk) then
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local ref = STMP.clkctrl.get_freq("clk_xtal")
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if HW.CLKCTRL.CPU.DIV_XTAL_FRAC_EN.read() == 1 then
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return ref * HW.CLKCTRL.CPU.DIV_XTAL.read() / 32
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else
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return ref / STMP.clkctrl.get_div(clk)
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end
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else
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local ref = STMP.clkctrl.get_freq("clk_pll")
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if STMP.clkctrl.get_frac_div(clk) ~= 0 then
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ref = ref * 18 / STMP.clkctrl.get_frac_div(clk)
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end
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return ref / STMP.clkctrl.get_div(clk)
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end
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else
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return STMP.CLKCTRL.get_freq("clk_pll") / STMP.clkctrl.get_div(clk)
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end
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elseif clk == "clk_hbus" then
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local ref = STMP.clkctrl.get_freq("clk_cpu")
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if hwstub.dev.stmp.chipid >= 0x3700 and STMP.clkctrl.get_frac_div(clk) ~= 0 then
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ref = ref * STMP.clkctrl.get_frac_div(clk) / 32
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end
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if STMP.clkctrl.get_div(clk) ~= 0 then
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ref = ref / STMP.clkctrl.get_div(clk)
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end
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return ref
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elseif clk == "clk_io" then
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local ref = STMP.clkctrl.get_freq("clk_pll")
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if hwstub.dev.stmp.chipid >= 0x3700 and STMP.clkctrl.get_frac_div(clk) ~= 0 then
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ref = ref * 18 / STMP.clkctrl.get_frac_div(clk)
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end
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return ref
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elseif hwstub.dev.stmp.chipid >= 0x3700 and clk == "clk_pix" then
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local ref = nil
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if not STMP.clkctrl.is_enabled(clk) then
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ref = 0
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elseif STMP.clkctrl.get_bypass(clk) then
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ref = STMP.clkctrl.get_freq("clk_xtal")
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else
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ref = STMP.clkctrl.get_freq("clk_pll")
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if STMP.clkctrl.get_frac_div(clk) ~= 0 then
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ref = ref * 18 / STMP.clkctrl.get_frac_div(clk)
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else
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ref = 0
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end
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end
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return ref / STMP.clkctrl.get_div(clk)
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elseif clk == "clk_ssp" then
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local ref = nil
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if not STMP.clkctrl.is_enabled(clk) then
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ref = 0
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elseif hwstub.dev.stmp.chipid >= 0x3700 and STMP.clkctrl.get_bypass(clk) then
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ref = STMP.clkctrl.get_freq("clk_xtal")
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else
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ref = STMP.clkctrl.get_freq("clk_io")
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end
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return ref / STMP.clkctrl.get_div(clk)
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elseif clk == "clk_emi" then
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if hwstub.dev.stmp.chipid >= 0x3700 then
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if STMP.clkctrl.get_bypass("clk_emi") then
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if HW.CLKCTRL.EMI.CLKGATE.read() then return 0
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else return STMP.clkctrl.get_freq("clk_xtal") / HW.CLKCTRL.EMI.DIV_XTAL.read() end
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else
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local ref = STMP.clkctrl.get_freq("clk_pll")
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if STMP.clkctrl.get_frac_div(clk) ~= 0 then
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ref = ref * 18 / STMP.clkctrl.get_frac_div(clk)
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end
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return ref / STMP.clkctrl.get_div(clk)
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end
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else
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return STMP.clkctrl.get_freq("clk_pll") / STMP.clkctrl.get_div(clk);
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end
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elseif clk == "clk_xbus" then
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return STMP.clkctrl.get_freq("clk_xtal") / STMP.clkctrl.get_div(clk)
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else
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return 0
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end
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end
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