427 lines
15 KiB
C
427 lines
15 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Largely taken from sdmaStruct.h from the Linux BSP provided by Freescale.
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* Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/* Other information gleaned from RE-ing the BSP and SDMA code */
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#ifndef SDMA_STRUCT_H
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#define SDMA_STRUCT_H
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/**
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* Number of channels
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*/
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#define CH_NUM 32
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/**
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* Ownership
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*/
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#define CH_OWNSHP_EVT (1 << 0)
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#define CH_OWNSHP_MCU (1 << 1)
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#if 0
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#define CH_OWNSHP_DSP (1 << 2)
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#endif
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/**
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* Channel contexts management
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*/
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/* Contexts for each channel begin here within SDMA core */
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#define CHANNEL_CONTEXT_BASE_ADDR 0x800
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/* Compute SDMA address where context for a channel is stored */
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#define CHANNEL_CONTEXT_ADDR(channel) \
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(CHANNEL_CONTEXT_BASE_ADDR+sizeof(struct context_data)/4*(channel))
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/**
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* Error bit set in the CCB status field by the SDMA,
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* in setbd routine, in case of a transfer error
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*/
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#define DATA_ERROR (1 << 28) /* BD_RROR set on last buffer descriptor */
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#define DATA_FAULT (1 << 29) /* A source or destination fault occured */
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/**
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* Buffer descriptor status values.
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*/
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#define BD_DONE 0x01 /* Set by host, cleared when SDMA has finished with
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this BD */
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#define BD_WRAP 0x02 /* If set in last descriptor, allows circular buffer
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* structure. curr_bd_ptr will be reset to base_bd_ptr
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*/
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#define BD_CONT 0x04 /* If set, more descriptors follow (multi-buffer) */
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#define BD_INTR 0x08 /* Interrupt when transfer complete */
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#define BD_RROR 0x10 /* Error during BD processing (set by SDMA) */
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#define BD_LAST 0x20 /* Set by SDMA ap_2_bp and bp_2_ap scripts.
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TODO: determine function */
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#define BD_EXTD 0x80 /* Use extended buffer address (indicates BD is 12
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bytes instead of 8) */
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/**
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* Buffer descriptor channel 0 commands.
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*/
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#define C0_SETCTX 0x07 /* Write context for a channel (ch# = BD command [7:3]) */
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#define C0_GETCTX 0x03 /* Read context for a channel (ch# = BD command [7:3]) */
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#define C0_SETDM 0x01 /* Write 32-bit words to SDMA memory */
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#define C0_GETDM 0x02 /* Read 32-bit words from SDMA memory */
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#define C0_SETPM 0x04 /* Write 16-bit halfwords to SDMA memory */
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#define C0_GETPM 0x08 /* Read 16-bit halfwords from SDMA memory */
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/* Treated the same as those above */
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#define C0_ADDR 0x01
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#define C0_LOAD 0x02
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#define C0_DUMP 0x03
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/**
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* Transfer sizes, encoded in the BD command field (when not a C0_ command).
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*/
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#define TRANSFER_32BIT 0x00
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#define TRANSFER_8BIT 0x01
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#define TRANSFER_16BIT 0x02
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#define TRANSFER_24BIT 0x03
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/**
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* Change endianness indicator in the BD command field
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*/
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#define CHANGE_ENDIANNESS 0x80
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/**
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* Size in bytes of struct buffer_descriptor
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*/
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#define SDMA_BD_SIZE 8
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#define SDMA_EXTENDED_BD_SIZE 12
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#define BD_NUMBER 4
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/**
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* Channel interrupt policy
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*/
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#define DEFAULT_POLL 0
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#define CALLBACK_ISR 1
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/**
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* Channel status
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*/
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#define UNINITIALIZED 0
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#define INITIALIZED 1
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/**
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* IoCtl particular values
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*/
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#define SET_BIT_ALL 0xFFFFFFFF
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#define BD_NUM_OFFSET 16
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#define BD_NUM_MASK 0xFFFF0000
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/**
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* Maximum values for IoCtl calls, used in high or middle level calls
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*/
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#define MAX_BD_NUM 256
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#define MAX_BD_SIZE 65536
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#define MAX_BLOCKING 2
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#define MAX_SYNCH 2
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#define MAX_OWNERSHIP 8
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#define MAX_CH_PRIORITY 8
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#define MAX_TRUST 2
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#define MAX_WML 256
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/**
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* Default values for channel descriptor - nobody owns the channel
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*/
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#define CD_DEFAULT_OWNERSHIP 7
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#if 0 /* IPC not used */
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/**
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* Data Node descriptor status values.
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*/
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#define DND_END_OF_FRAME 0x80
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#define DND_END_OF_XFER 0x40
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#define DND_DONE 0x20
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#define DND_UNUSED 0x01
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/**
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* IPCV2 descriptor status values.
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*/
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#define BD_IPCV2_END_OF_FRAME 0x40
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#define IPCV2_MAX_NODES 50
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/**
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* User Type Section
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*/
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/**
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* Command/Mode/Count of buffer descriptors
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*/
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struct mode_count_ipcv2
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{
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unsigned long count : 16; /* size of the buffer pointed by this BD */
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unsigned long reserved : 8; /* reserved */
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unsigned long status : 8; /* L, E, D bits stored here */
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};
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/**
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* Data Node descriptor - IPCv2
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* (differentiated between evolutions of SDMA)
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*/
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struct data_node_descriptor
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{
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struct mode_count_ipcv2 mode; /* command, status and count */
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void* buffer_addr; /* address of the buffer described */
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};
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struct mode_count_ipcv1_v2
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{
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unsigned long count : 16; /* size of the buffer pointed by this BD */
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unsigned long status : 8; /* E,R,I,C,W,D status bits stored here */
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unsigned long reserved : 7;
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unsigned long endianness : 1;
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};
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/**
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* Buffer descriptor
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* (differentiated between evolutions of SDMA)
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*/
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struct buffer_descriptor_ipcv1_v2
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{
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struct mode_count_ipcv1_v2 mode; /* command, status and count */
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void *buffer_addr; /* address of the buffer described */
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void *ext_buffer_addr; /* extended buffer address */
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};
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#endif /* No IPC */
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/**
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* Mode/Count of data node descriptors - IPCv2
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*/
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struct mode_count
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{
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unsigned long count : 16; /* size of the buffer pointed by this BD */
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unsigned long status : 8; /* E,R,I,C,W,D status bits stored here:
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* SDMA r/w */
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unsigned long command : 8; /* channel 0 command or transfer size */
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};
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/**
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* Buffer descriptor - describes each buffer in a DMA transfer.
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* (differentiated between evolutions of SDMA)
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*/
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/* (mode.status & BD_EXTD) == 0 (8 bytes) */
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struct buffer_descriptor
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{
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volatile struct mode_count mode; /* command, status and count: SDMA r/w */
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void *buf_addr; /* address of the buffer described: SDMA r */
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};
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/* (mode.status & BD_EXTD) != 0 (12 bytes) */
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struct buffer_descriptor_extd
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{
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struct buffer_descriptor bd;
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void *buf_addr_ext; /* extended buffer address described (r6): SDMA r */
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};
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#if 0 /* A different one is defined for Rockbox use - this has too much.
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* See below. */
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struct channel_control_block;
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struct channel_descriptor;
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/**
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* Channel Descriptor
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*/
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struct channel_descriptor
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{
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unsigned char channel_number; /* stores the channel number */
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unsigned char buffer_desc_count; /* number of BD's allocated
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for this channel */
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unsigned short buffer_per_desc_size; /* size (in bytes) of buffer
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descriptors' data buffers */
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unsigned long blocking : 3; /* polling/ callback method
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selection */
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unsigned long callback_synch : 1; /* (iapi) blocking / non blocking
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feature selection */
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unsigned long ownership : 3; /* ownership of the channel
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(host+dedicated+event) */
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unsigned long priority : 3; /* reflects the SDMA channel
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priority register */
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unsigned long trust : 1; /* trusted buffers or kernel
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allocated */
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unsigned long use_data_size : 1; /* (iapi) indicates if the dataSize
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field is meaningfull */
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unsigned long data_size : 2; /* (iapi->BD) data transfer
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size - 8,16,24 or 32 bits*/
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unsigned long force_close : 1; /* If TRUE, close channel even
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with BD owned by SDMA*/
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unsigned long script_id : 7; /* number of the script */
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unsigned long watermark_level : 10; /* (greg) Watermark level for the
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peripheral access */
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unsigned long event_mask1; /* (greg) First Event mask */
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unsigned long event_mask2; /* (greg) Second Event mask */
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unsigned long shp_addr; /* (greg) Address of the peripheral
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or its fifo when needed */
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void (* callback)(struct channel_descriptor *); /* pointer to the
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callback function (or NULL) */
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struct channel_control_block *ccb_ptr; /* pointer to the channel control
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block associated to this
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channel */
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};
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#endif
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/* Only what we need, members sorted by size, no code-bloating bitfields */
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struct channel_descriptor
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{
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unsigned int bd_count; /* number of BD's allocated
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for this channel */
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struct channel_control_block *ccb_ptr; /* pointer to the channel control
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block associated to this
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channel */
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void (* callback)(void); /* pointer to the
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callback function (or NULL) */
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unsigned long shp_addr; /* (greg) Address of the peripheral
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or its fifo when needed */
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unsigned short wml; /* (greg) Watermark level for the
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peripheral access */
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unsigned char per_type; /* Peripheral type */
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unsigned char tran_type; /* Transfer type */
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unsigned char event_id1; /* DMA request ID */
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unsigned char event_id2; /* DMA request ID 2 */
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unsigned char is_setup; /* Channel setup has been done */
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};
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/**
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* Channel Status
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*/
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struct channel_status
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{
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unsigned long unused : 28;
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unsigned long error : 1; /* Last BD triggered an error:
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SDMA r/w */
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unsigned long opened_init : 1; /* Channel is initialized:
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SDMA r/w */
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unsigned long state_direction : 1; /* SDMA is reading/writing (as seen
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from channel owner core) */
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unsigned long execute : 1; /* Channel is being processed
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(started) or not */
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};
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/**
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* Channel control Block
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* SDMA ROM code expects these are 16-bytes each in an array
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* (MC0PTR + 16*CCR)
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*/
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struct channel_control_block
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{
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/* current buffer descriptor processed: SDMA r/w */
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struct buffer_descriptor * volatile curr_bd_ptr;
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/* first element of buffer descriptor array: SDMA r */
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struct buffer_descriptor *base_bd_ptr;
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/* pointer to the channel descriptor: SDMA ignored */
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struct channel_descriptor *channel_desc;
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/* open/close ; started/stopped ; read/write: SDMA r/w */
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volatile struct channel_status status;
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};
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/**
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* Channel context structure.
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*/
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/* Channel state bits on SDMA core side */
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struct state_registers
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{
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/* Offset 0 */
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unsigned long pc : 14; /* program counter */
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unsigned long unused0 : 1;
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unsigned long t : 1; /* test bit: status of arithmetic & test
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instruction */
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unsigned long rpc : 14; /* return program counter */
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unsigned long unused1 : 1;
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unsigned long sf : 1; /* source fault while loading data */
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/* Offset 1 */
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unsigned long spc : 14; /* loop start program counter */
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unsigned long unused2 : 1;
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unsigned long df : 1; /* destination falut while storing data */
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unsigned long epc : 14; /* loop end program counter */
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unsigned long lm : 2; /* loop mode */
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};
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/* Context data saved for every channel on the SDMA core. This is 32 words
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* long which is specified in the SDMA initialization on the AP side. The
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* SDMA scripts utilize the scratch space. */
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struct context_data
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{
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struct state_registers channel_state; /* channel state bits */
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union
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{
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unsigned long r[8]; /* general registers (r0-r7) */
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struct /* script usage of said when
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setting contexts */
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{
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unsigned long event_mask2; /* 08h */
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unsigned long event_mask1; /* 0Ch */
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unsigned long r2; /* 10h */
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unsigned long r3; /* 14h */
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unsigned long r4; /* 18h */
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unsigned long r5; /* 1Ch */
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unsigned long shp_addr; /* 20h */
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unsigned long wml; /* 24h */
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|
|
};
|
||
|
|
};
|
||
|
|
unsigned long mda; /* burst dma destination address register */
|
||
|
|
unsigned long msa; /* burst dma source address register */
|
||
|
|
unsigned long ms; /* burst dma status register */
|
||
|
|
unsigned long md; /* burst dma data register */
|
||
|
|
unsigned long pda; /* peripheral dma destination address register */
|
||
|
|
unsigned long psa; /* peripheral dma source address register */
|
||
|
|
unsigned long ps; /* peripheral dma status register */
|
||
|
|
unsigned long pd; /* peripheral dma data register */
|
||
|
|
unsigned long ca; /* CRC polynomial register */
|
||
|
|
unsigned long cs; /* CRC accumulator register */
|
||
|
|
unsigned long dda; /* dedicated core destination address register */
|
||
|
|
unsigned long dsa; /* dedicated core source address register */
|
||
|
|
unsigned long ds; /* dedicated core status register */
|
||
|
|
unsigned long dd; /* dedicated core data register */
|
||
|
|
unsigned long scratch[8]; /* channel context scratch RAM */
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This structure holds the necessary data for the assignment in the
|
||
|
|
* dynamic channel-script association
|
||
|
|
*/
|
||
|
|
struct script_data
|
||
|
|
{
|
||
|
|
unsigned long load_address; /* start address of the script */
|
||
|
|
unsigned long wml; /* parameters for the channel descriptor */
|
||
|
|
unsigned long shp_addr; /* shared peripheral base address */
|
||
|
|
unsigned long event_mask1; /* first event mask */
|
||
|
|
unsigned long event_mask2; /* second event mask */
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This structure holds the the useful bits of the CONFIG register
|
||
|
|
*/
|
||
|
|
struct configs_data
|
||
|
|
{
|
||
|
|
unsigned long dspdma : 1; /* indicates if the DSPDMA is used */
|
||
|
|
unsigned long rtdobs : 1; /* indicates if Real-Time Debug pins are
|
||
|
|
enabled */
|
||
|
|
unsigned long acr : 1; /* indicates if AHB freq /core freq = 2 or 1 */
|
||
|
|
unsigned long csm : 2; /* indicates which context switch mode is
|
||
|
|
selected */
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* SDMA_STRUCT_H */
|