98 lines
2.5 KiB
ArmAsm
98 lines
2.5 KiB
ArmAsm
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "mips.h"
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.text
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.extern spl_main
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.global _spl_start
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.set push
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.set mips32
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.set noreorder
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.set noat
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.section .init.spl
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_spl_start:
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/* Clear data watchpoint */
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mtc0 zero, C0_WATCHLO
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mtc0 zero, C0_WATCHHI
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/* Set BEV, ERL, mask interrupts */
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li v0, 0x40fc04
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mtc0 v0, C0_Status
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/* Set Cause_IV to 1 (use special interrupt vector) */
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li v0, M_CauseIV
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mtc0 v0, C0_Cause
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/* Set CPU_MODE and BUS_MODE to 1 in CPM_OPCR (Ingenic does this) */
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lui v0, 0xb000
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lw v1, 0x24(v0)
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ori v1, v1, 0x22
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sw v1, 0x24(v0)
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/* Enable kseg0 cacheability */
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li v0, 3
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mtc0 v0, C0_Config
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nop
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/* According to ingenic: "enable idx-store-data cache insn" */
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li v0, 0x20000000
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mtc0 v0, C0_ErrCtl
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/* Cache init */
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li v0, 0x80000000
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ori v1, v0, 0x4000
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mtc0 zero, C0_TAGLO
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mtc0 zero, C0_TAGHI
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_cache_loop:
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cache ICIndexStTag, 0(v0)
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cache DCIndexStTag, 0(v0)
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addiu v0, v0, 32
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bne v0, v1, _cache_loop
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nop
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/* Invalidate BTB */
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mfc0 v0, C0_Config, 7
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nop
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ori v0, v0, 2
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mtc0 v0, C0_Config, 7
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nop
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/* Clear the BSS segment (needed to zero-initialize C static values) */
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la t0, _bssbegin
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la t1, _bssend
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beq t0, t1, _bss_done
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_bss_loop:
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addiu t0, 4
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bne t0, t1, _bss_loop
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sw zero, -4(t0)
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_bss_done:
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/* Jump to C code */
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j spl_main
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nop
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.set pop
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