2018-06-28 10:24:26 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2016 by Roman Stolyarov
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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2020-09-06 00:15:23 +00:00
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2018-06-28 10:24:26 +00:00
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#include "config.h"
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#include "cpu.h"
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#include "system.h"
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#include "timer.h"
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2020-09-06 00:15:23 +00:00
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#define TIMER_ID 5
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2018-06-28 10:24:26 +00:00
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/* Interrupt handler */
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void TCU1(void)
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{
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2020-09-06 00:15:23 +00:00
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__tcu_clear_full_match_flag(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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if (pfn_timer != NULL)
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pfn_timer();
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}
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bool timer_set(long cycles, bool start)
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{
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unsigned int divider = cycles, prescaler_bit = 0, prescaler = 1, old_irq;
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if(cycles < 1)
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return false;
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if(start && pfn_unregister != NULL)
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{
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pfn_unregister();
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pfn_unregister = NULL;
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}
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/* Increase prescale values starting from 0 to make the cycle count fit */
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while(divider > 65535 && prescaler <= 1024)
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{
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prescaler <<= 2; /* 1, 4, 16, 64, 256, 1024 */
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prescaler_bit++;
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divider = cycles / prescaler;
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}
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old_irq = disable_irq_save();
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2020-09-06 00:15:23 +00:00
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__tcu_stop_counter(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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if(start)
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{
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2020-09-06 00:15:23 +00:00
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__tcu_disable_pwm_output(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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2020-09-06 00:15:23 +00:00
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__tcu_mask_half_match_irq(TIMER_ID);
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__tcu_unmask_full_match_irq(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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/* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */
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2020-09-06 00:15:23 +00:00
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__tcu_select_extalclk(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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}
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2020-09-06 00:15:23 +00:00
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REG_TCU_TCSR(TIMER_ID) = (REG_TCU_TCSR(TIMER_ID) & ~TCSR_PRESCALE_MASK) | (prescaler_bit << TCSR_PRESCALE_LSB);
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REG_TCU_TCNT(TIMER_ID) = 0;
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REG_TCU_TDHR(TIMER_ID) = 0;
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REG_TCU_TDFR(TIMER_ID) = divider;
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2018-06-28 10:24:26 +00:00
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2020-09-06 00:15:23 +00:00
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__tcu_clear_full_match_flag(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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if(start)
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{
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system_enable_irq(IRQ_TCU1);
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}
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restore_irq(old_irq);
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2020-09-06 00:15:23 +00:00
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__tcu_start_counter(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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return true;
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}
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bool timer_start(void)
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{
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2020-09-06 00:15:23 +00:00
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__tcu_start_counter(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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return true;
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}
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void timer_stop(void)
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{
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unsigned int old_irq = disable_irq_save();
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2020-09-06 00:15:23 +00:00
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__tcu_stop_counter(TIMER_ID);
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2018-06-28 10:24:26 +00:00
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restore_irq(old_irq);
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}
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