110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 Bertrik Sikken
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <string.h>
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#include "config.h"
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#include "s5l8700.h"
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#include "nand-target.h"
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/* Driver for the S5L8700 flash memory controller for low-level access to the
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NAND flash of the Samsung YP-S3.
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The YP-S3 seems to use the pins P6.5 and P6.6 as chip selects in GPIO mode
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instead of using the regular pins P6.3 and P6.4.
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*/
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#define FMSTAT_RBB (1<<0)
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#define FMSTAT_RBBDone (1<<1)
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#define FMSTAT_CMDDone (1<<2)
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#define FMSTAT_AddrDone (1<<3)
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#define FMSTAT_TransDone (1<<4)
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#define FMSTAT_WFIFO_HEMPTY (1<<5)
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#define FMSTAT_RFIFO_HFULL (1<<6)
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#define FMSTAT_WFIFO_EMPTY (1<<8)
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#define FMSTAT_RFIFO_FULL (1<<9)
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#define FMSTAT_EndECC (1<<10)
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#define FMCTRL1_DoTransAddr (1<<0)
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#define FMCTRL1_DoReadData (1<<1)
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#define FMCTRL1_DoWriteData (1<<2)
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#define FMCTRL1_WriteREQSEL (1<<4)
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#define FMCTRL1_ClearSyndPtr (1<<5)
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#define FMCTRL1_ClearWFIFO (1<<6)
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#define FMCTRL1_ClearRFIFO (1<<7)
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#define FMCTRL1_ParityPtr (1<<8)
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#define FMCTRL1_SyndPtr (1<<9)
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static void nand_chip_select(int bank)
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{
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unsigned int select;
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select = (1 << bank);
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FMCTRL0 = 0x1821 | ((select & 3) << 1);
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PDAT6 = (PDAT6 & ~0x60) | ((~select & 0xC) << 3);
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}
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void nand_ll_init(void)
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{
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/* enable flash memory controller */
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PWRCON &= ~(1 << 1);
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/* P2.X is SMC I/O */
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PCON2 = 0x55555555;
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/* P4.1 = CLE, P4.4 = nWR, P4.5 = nRD */
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PCON4 = (PCON4 & ~0x00FF00F0) | 0x00550050;
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/* P6.0 = nf_rbn, P6.1 = smc_ce0, P6.2 = smc_ce1,
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P6.5 = smc_ce2 (as GPIO), P6.6 = smc_ce3 (as GPIO), P6.7 = ALE */
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PCON6 = (PCON6 & ~0xFFF00FFF) | 0x51100555;
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PDAT6 |= 0x60;
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}
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unsigned int nand_ll_read_id(int bank)
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{
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unsigned int nand_id;
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nand_chip_select(bank);
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/* send "read id" command */
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FMCMD = 0x90;
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while ((FMCSTAT & FMSTAT_CMDDone) == 0);
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FMCSTAT = FMSTAT_CMDDone;
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/* transfer address */
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FMANUM = 0;
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FMADDR0 = 0;
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FMCTRL1 = FMCTRL1_DoTransAddr;
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while ((FMCSTAT & FMSTAT_AddrDone) == 0);
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FMCSTAT = FMSTAT_AddrDone;
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/* read back data */
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FMDNUM = 3;
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FMCTRL1 = FMCTRL1_DoReadData;
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while ((FMCSTAT & FMSTAT_TransDone) == 0);
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FMCSTAT = FMSTAT_TransDone;
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nand_id = FMFIFO;
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/* clear read FIFO */
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FMCTRL1 = FMCTRL1_ClearRFIFO;
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return nand_id;
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}
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