275 lines
9.5 KiB
ArmAsm
275 lines
9.5 KiB
ArmAsm
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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*
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* Copyright (C) 2009 by Jorge Pinto
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "at91sam9260.h"
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#define DRAMORIG AT91C_EBI_SDRAM_32BIT
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#define DRAMSIZE (MEMORYSIZE * 0x100000)
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#define IRAM0ORIG AT91C_IRAM_1
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#define IRAM0SIZE AT91C_IRAM_1_SIZE
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#define TOP_OF_MEMORY (IRAM0ORIG + IRAM0SIZE)
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#define ABT_STACK_SIZE 8*3*4
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#define IRQ_STACK_SIZE 8*3*4
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#define ARM_MODE_ABT 0x17
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#define ARM_MODE_FIQ 0x11
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#define ARM_MODE_IRQ 0x12
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#define ARM_MODE_SVC 0x13
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#define I_BIT 0x80
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#define F_BIT 0x40
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/* Application startup entry point */
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.globl reset_handler
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.align 4
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.section .vectors
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.arm
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/* Exception vectors (should be a branch to be detected as a valid code
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* by the rom) */
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_exception_vectors:
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reset_vector:
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ldr pc, =reset_handler
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undef_vector:
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b undef_vector /* Undefined Instruction */
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swi_vector:
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b swi_vector /* Software Interrupt */
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pabt_vector:
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ldr pc, =pabt_handler /* Prefetch Abort */
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dabt_vector:
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ldr pc, =dabt_handler /* Data Abort */
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rsvd_vector:
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b rsvd_vector /* reserved */
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irq_vector:
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b irq_handler /* IRQ : read the AIC */
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fiq_vector:
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/*-----------------------------------------------------------------------------
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*- Function : fiq_handler
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*- Treatments : FIQ (Fast Interrupt) Interrupt Handler.
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*- Called Functions :
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*---------------------------------------------------------------------------*/
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fiq_handler:
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pabt_handler:
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dabt_handler:
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b fiq_handler
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/*-----------------------------------------------------------------------------
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*- Function : irq_handler
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*- Treatments : IRQ Controller Interrupt Handler.
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*- Called Functions : AIC_IVR[interrupt]
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*---------------------------------------------------------------------------*/
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irq_handler:
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/*- Manage Exception Entry */
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/*- Adjust and save LR_irq in IRQ stack - (LR - Link Register) */
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sub lr, lr, #4
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stmfd sp!, {lr}
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/*- Save r0 and SPSR (Saved Program Status Register) in IRQ stack */
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mrs r14, SPSR
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stmfd sp!, {r0,r14}
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/*- Write in the IVR (Interrupt Vector Register) to support Protect Mode */
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/*- No effect in Normal Mode */
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/*- De-assert the NIRQ and clear the source in Protect Mode */
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ldr r14, =AT91C_BASE_AIC
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ldr r0 , [r14, #AIC_IVR]
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str r14, [r14, #AIC_IVR]
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/*- Enable Interrupt and Switch in Supervisor Mode */
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msr CPSR_c, #ARM_MODE_SVC
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/*- Save scratch/used registers and LR in User Stack */
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stmfd sp!, {r1-r3, r12, r14}
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/*- Branch to the routine pointed by the AIC_IVR */
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mov r14, pc
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bx r0
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/*- Restore scratch/used registers and LR from User Stack */
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ldmia sp!, {r1-r3, r12, r14}
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/*- Disable Interrupt and switch back in IRQ mode */
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT
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/*- Mark the End of Interrupt on the AIC */
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ldr r14, =AT91C_BASE_AIC
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str r14, [r14, #AIC_EOICR]
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/*- Restore SPSR_irq and r0 from IRQ stack */
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ldmia sp!, {r0,r14}
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msr SPSR_cxsf, r14
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/*- Restore adjusted LR_irq from IRQ stack directly in the PC */
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ldmia sp!, {pc}^
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/*-----------------------------------------------------------------------------
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*- Function : reset_handler
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*- Treatments : Reset Interrupt Handler.
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*- Called Functions : lowlevel_init
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* main
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*---------------------------------------------------------------------------*/
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.section .text
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reset_handler:
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/*-----------------------------------------------------------------------------
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*- Low level Init is performed in a C function: lowlevel_init
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*- Init Stack Pointer to a valid memory area before calling lowlevel_init
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*
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* Put Stack Pointer on end of IRAM 1 and branches to lowlevel_init function.
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*---------------------------------------------------------------------------*/
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/*- Temporary stack in internal RAM for Low Level Init execution */
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_low_level_init:
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ldr r2, =_litteral_pool_lowlevel_init /* Load r2 with the address of
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* _litteral_pool_lowlevel_init
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*/
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ldmia r2, {r0, r1} /* r0 = lowlevel_init and r1 = TOP_OF_MEMORY */
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mov sp, r1 /* sp (Stack Pointer) = TOP_OF_MEMORY (end of IRAM 1) */
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mov lr, pc /* lr (Link register) = pc (Program Counter) */
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bx r0 /* Branch on C function (interworking) -- branch to
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* lowlevel_init
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*/
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/*-----------------------------------------------------------------------------
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*- Setup the stack for each mode
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*
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* Executes this code after returning from lowlevel_init fucntion.
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* Configures Abort Mode Stack + Interrupt Mode Stack + Supervisor Mode Stack,
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* reserves 3 blocks, one for each mode and they start at end of IRAM 1.
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*---------------------------------------------------------------------------*/
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_stack_init:
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ldr r2, =_litteral_pool_stack_init
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ldmia r2, {r0, r1, r2} /* r0 = TOP_OF_MEMORY (end of IRAM 1);
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* r1 = ABT_STACK_SIZE;
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* r2 = IRQ_STACK_SIZE
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*/
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/*- Set up Abort Mode and set ABT Mode Stack */
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT /* Enter in Mode Abort
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* and disable IRQ (Interrupt) and FIQ (Fast Interrupt)
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*/
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mov sp, r0 /* sp (ABT Mode Stack Pointer) = TOP_OF_MEMORY
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* (end of IRAM 1)
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*/
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/* put r0 with value of the new address for next Stack */
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sub r0, r0, r1 /* r0 = r0 - r1 --> r0 = (end of IRAM 1) -
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* (ABT_STACK_SIZE)
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*/
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/*- Set up Interrupt Mode and set IRQ Mode Stack */
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* Enter in Mode Interrupt
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* and disable IRQ (Interrupt) and FIQ (Fast Interrupt)
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*/
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mov sp, r0 /* sp (Interrupt Mode Stack Pointer) =
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* TOP_OF_MEMORY (end of IRAM 1) - (ABT_STACK_SIZE)
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*/
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sub r0, r0, r2 /* Put on r0 the new address for next
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* Stack (Supervisor Mode)
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*/
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/*- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack */
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msr CPSR_c, #ARM_MODE_SVC | F_BIT
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mov sp, r0
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/*-----------------------------------------------------------------------------
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*- Segments initialization
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*---------------------------------------------------------------------------*/
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/* Copy the vectors section code from the LMA address to the LVA address */
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_init_vectors:
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ldr r1, =_litteral_pool_vectors /* Load r1 with the address of
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* _litteral_pool_vectors
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*/
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ldmia r1, {r2, r3, r4} /* r2 = DRAMORIG; r3 = _start_vectors_section;
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* r4 = _end_vectors_section;
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*/
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1:
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cmp r3, r4 /* Compare r3 with r4 (r3 - r4) */
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ldrcc r5, [r2], #4 /* if (_start_vectors_section < _end_vectors_section)
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* { r5 = [r2]; r2 = r2 + 4; }
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*/
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strcc r5, [r3], #4 /* if (_start_vectors_section < _end_vectors_section)
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* { [r3] = r5; r3 = r3 + 4; }
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*/
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bcc 1b /* loop while (_start_vectors_section < _end_vectors_section) */
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/* Clear the bss segment */
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_init_bss:
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ldr r2, =_litteral_pool_bss
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ldmia r2, {r3, r4} /* r3 = _start_bss_section; r4 = _end_bss_section */
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mov r2, #0 /* r2 = 0 */
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1:
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cmp r3, r4 /* Compare --> (_start_bss_section - _end_bss_section) */
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strcc r2, [r3], #4 /* if (_start_bss_section < _end_bss_section) {
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* [r3] = 0; r3 = r3 + 4; }
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*/
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bcc 1b /* loop while _start_bss_section < _end_bss_section */
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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mov r3, sp
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ldr r2, =stackbegin
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ldr r4, =0xdeadbeef
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stackmunge:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi stackmunge
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/*-----------------------------------------------------------------------------
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*- Branch to the main
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*---------------------------------------------------------------------------*/
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_branch_main:
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ldr r0, =main
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mov lr, pc
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bx r0
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/*-----------------------------------------------------------------------------
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*- Litteral pools
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*---------------------------------------------------------------------------*/
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_litteral_pool_lowlevel_init:
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.word lowlevel_init
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.word TOP_OF_MEMORY /* Default SVC stack after power up */
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_litteral_pool_stack_init:
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.word TOP_OF_MEMORY /* Top of the stack */
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.word ABT_STACK_SIZE /* ABT stack size */
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.word IRQ_STACK_SIZE /* IRQ stack size */
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_litteral_pool_bss:
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.word _start_bss_section
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.word _end_bss_section
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_litteral_pool_vectors:
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#if defined(BOOTLOADER)
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.word (DRAMORIG + DRAMSIZE - 0x100000) /* LMA address of vectors are at
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* end of DRAM minus 1MByte
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*/
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#else
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.word DRAMORIG /* LMA address of vectors are at DRAMORIG */
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#endif
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.word _start_vectors_section
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.word _end_vectors_section
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