2021-04-26 21:57:31 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __X1000_H__
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#define __X1000_H__
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#include "config.h"
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/* Frequency of external oscillator EXCLK */
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//#define X1000_EXCLK_FREQ 24000000
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/* Maximum CPU frequency that can be achieved on the target */
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//#define CPU_FREQ 1008000000
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/* Only 24 MHz and 26 MHz external oscillators are supported by the X1000 */
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#if X1000_EXCLK_FREQ == 24000000
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# define X1000_EXCLK_24MHZ
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#elif X1000_EXCLK_FREQ == 26000000
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# define X1000_EXCLK_26MHZ
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#else
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# error "Unsupported EXCLK freq"
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#endif
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/* On-chip TCSM (tightly coupled shared memory), aka IRAM */
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#define X1000_TCSM_BASE 0xf4000000
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#define X1000_TCSM_SIZE (16 * 1024)
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/* External SDRAM */
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#define X1000_SDRAM_BASE 0x80000000
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#define X1000_SDRAM_SIZE (MEMORYSIZE * 1024 * 1024)
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/* Memory definitions for Rockbox */
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#define X1000_IRAM_BASE X1000_SDRAM_BASE
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#define X1000_IRAM_SIZE (16 * 1024)
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#define X1000_IRAM_END (X1000_IRAM_BASE + X1000_IRAM_SIZE)
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#define X1000_DRAM_BASE X1000_IRAM_END
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#define X1000_DRAM_SIZE (X1000_SDRAM_SIZE - X1000_IRAM_SIZE)
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#define X1000_DRAM_END (X1000_DRAM_BASE + X1000_DRAM_SIZE)
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#define X1000_STACKSIZE 0x1e00
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#define X1000_IRQSTACKSIZE 0x300
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2022-03-03 19:56:26 +00:00
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/* Standard DRAM base address for backward compatibility */
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#define X1000_STANDARD_DRAM_BASE 0x80004000
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2022-01-11 13:56:46 +00:00
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/* Required for pcm_rec_dma_get_peak_buffer(), doesn't do anything
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* except on targets with recording. */
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#define HAVE_PCM_DMA_ADDRESS
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#define HAVE_PCM_REC_DMA_ADDRESS
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2021-04-26 21:57:31 +00:00
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/* Convert kseg0 address to physical address or uncached address */
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#define PHYSADDR(x) ((unsigned long)(x) & 0x1fffffff)
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#define UNCACHEDADDR(x) (PHYSADDR(x) | 0xa0000000)
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/* Defines for usb-designware driver */
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#define OTGBASE 0xb3500000
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#define USB_NUM_ENDPOINTS 9
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/* CPU cache parameters */
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#define CACHEALIGN_BITS 5
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#define CACHE_SIZE (16 * 1024)
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#endif /* __X1000_H__ */
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