99 lines
3.2 KiB
ArmAsm
99 lines
3.2 KiB
ArmAsm
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#include "mips.h"
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.extern main
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.global start
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.set mips32
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.set noreorder
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.set noat
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.section .init.text,"ax",%progbits
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/* WARNING
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* We have no idea where the stubs starts running, there basically are three cases:
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* - tcsm0: the stub is already at the right place, nothing do to
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* - ram: sdram/ddram is active and we just need to move the stub
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* - cache: the bootrom put us in cache-as-ram, we need to be careful
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* Note that that those are initially quite different because:
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* - tcsm0 is uncached
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* - ram is almost always cached when we are running from it
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* - cache-as-ram is cached but the cache is the only copy of our code and the
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* icache was prefilled from dcache by the bootrom using some mips magic
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*
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* This means we have to be very careful with the cache because if we flush the
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* icache in the cache-as-cache case, we cannot refill it, and worse, we cannot
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* commit the dcache either because the ram might not even be initialised. Thus
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* the only safe option in all cases is to copy the stub to an *uncached* location
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* so that we don't have to commit the dcache and the icache can safely read from
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* it.
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*/
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start:
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bltzal zero, load_addr /* ra = PC + 8, branch not taken */
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nop
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load_addr:
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addiu v0, ra, -8 /* calc real load address
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account for branch delay slot */
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move k0, v0 /* store starting location to give it to main */
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la t0, relocstart /* relocate code if needed */
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la t1, relocend
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beq t0, v0, clear_bss /* no relocation needed */
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nop
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reloc_loop:
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lw s0, 0(v0) /* v0 = src */
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lw s1, 4(v0)
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lw s2, 8(v0)
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lw s3, 12(v0)
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sw s0, 0(t0) /* t0 = dst */
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sw s1, 4(t0)
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sw s2, 8(t0)
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sw s3, 12(t0)
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/* Tricky part: as explained earlier, tcsm0 is uncached so no need to commit
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* the dcache but we want to invalidate the icache ONLY AT THIS LOCATION.
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* Indeed, if the invalidate the entire icache in the cache-as-ram case, we
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* will miserably crash */
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cache ICHitInv, 0(t0) /* invalidate virtual address in icache */
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addiu t0, t0, 16 /* inc dst addr */
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slt t2, t0, t1
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bnez t2, reloc_loop
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addiu v0, v0, 16 /* inc src addr */
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/* jump to tcsm0 */
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la t0, tcsm0_entry
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jr t0
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sync
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tcsm0_entry:
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/* now that we are running from tcsm0, which is uncached, we can finally
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* properly invalidate all caches just to be sure */
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mtc0 zero, C0_TagLo
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mtc0 zero, C0_DataLo
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la t0, 0x80000000 /* an idx op should use an unmappable address */
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ori t1, t0, 0x4000 /* 16kB cache */
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cache_inv_loop:
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cache ICIndexStTag, 0(t0) /* index store icache tag */
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cache DCIndexStTag, 0(t0) /* index store dcache tag */
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bne t0, t1, cache_inv_loop
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addiu t0, 0x20 /* 32 bytes per line */
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clear_bss:
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la t0, bssbegin
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la t1, bssend
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beq t0, t1, stack_setup
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nop
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clear_bss_loop:
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sw zero, 0(t0)
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bne t0, t1, clear_bss_loop
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addiu t0, 4
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stack_setup:
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la sp, oc_stackend
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/* jump to C code */
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la t0, main
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jr t0
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move a0, k0
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