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rockbox/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h

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imx233: generate register headers for stmp3600, stmp3700 and imx233 Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
2013-06-13 17:03:33 +00:00
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
imx233: regenerate headers Change-Id: I9dae85eb27337154ddb82015666773a5254cc388
2014-02-18 17:19:44 +00:00
* headergen version: 2.1.8
imx233: generate register headers for stmp3600, stmp3700 and imx233 Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
2013-06-13 17:03:33 +00:00
* XML versions: stmp3600:2.3.0
*
* Copyright (C) 2013 by Amaury Pouly
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN__STMP3600__IR__H__
#define __HEADERGEN__STMP3600__IR__H__
#define REGS_IR_BASE (0x80078000)
#define REGS_IR_VERSION "2.3.0"
/**
* Register: HW_IR_CTRL
* Address: 0
* SCT: yes
*/
#define HW_IR_CTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0))
#define HW_IR_CTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4))
#define HW_IR_CTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8))
#define HW_IR_CTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc))
#define BP_IR_CTRL_SFTRST 31
#define BM_IR_CTRL_SFTRST 0x80000000
#define BV_IR_CTRL_SFTRST__RUN 0x0
#define BV_IR_CTRL_SFTRST__RESET 0x1
#define BF_IR_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
#define BF_IR_CTRL_SFTRST_V(v) ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000)
#define BP_IR_CTRL_CLKGATE 30
#define BM_IR_CTRL_CLKGATE 0x40000000
#define BF_IR_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
#define BP_IR_CTRL_MTA 24
#define BM_IR_CTRL_MTA 0x7000000
#define BV_IR_CTRL_MTA__MTA_10MS 0x0
#define BV_IR_CTRL_MTA__MTA_5MS 0x1
#define BV_IR_CTRL_MTA__MTA_1MS 0x2
#define BV_IR_CTRL_MTA__MTA_500US 0x3
#define BV_IR_CTRL_MTA__MTA_100US 0x4
#define BV_IR_CTRL_MTA__MTA_50US 0x5
#define BV_IR_CTRL_MTA__MTA_10US 0x6
#define BV_IR_CTRL_MTA__MTA_0 0x7
#define BF_IR_CTRL_MTA(v) (((v) << 24) & 0x7000000)
#define BF_IR_CTRL_MTA_V(v) ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000)
#define BP_IR_CTRL_MODE 22
#define BM_IR_CTRL_MODE 0xc00000
#define BV_IR_CTRL_MODE__SIR 0x0
#define BV_IR_CTRL_MODE__MIR 0x1
#define BV_IR_CTRL_MODE__FIR 0x2
#define BV_IR_CTRL_MODE__VFIR 0x3
#define BF_IR_CTRL_MODE(v) (((v) << 22) & 0xc00000)
#define BF_IR_CTRL_MODE_V(v) ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000)
#define BP_IR_CTRL_SPEED 19
#define BM_IR_CTRL_SPEED 0x380000
#define BV_IR_CTRL_SPEED__SPD000 0x0
#define BV_IR_CTRL_SPEED__SPD001 0x1
#define BV_IR_CTRL_SPEED__SPD010 0x2
#define BV_IR_CTRL_SPEED__SPD011 0x3
#define BV_IR_CTRL_SPEED__SPD100 0x4
#define BV_IR_CTRL_SPEED__SPD101 0x5
#define BF_IR_CTRL_SPEED(v) (((v) << 19) & 0x380000)
#define BF_IR_CTRL_SPEED_V(v) ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000)
#define BP_IR_CTRL_TC_TIME_DIV 8
#define BM_IR_CTRL_TC_TIME_DIV 0x3f00
#define BF_IR_CTRL_TC_TIME_DIV(v) (((v) << 8) & 0x3f00)
#define BP_IR_CTRL_TC_TYPE 7
#define BM_IR_CTRL_TC_TYPE 0x80
#define BF_IR_CTRL_TC_TYPE(v) (((v) << 7) & 0x80)
#define BP_IR_CTRL_SIR_GAP 4
#define BM_IR_CTRL_SIR_GAP 0x70
#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
#define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1
#define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2
#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
#define BV_IR_CTRL_SIR_GAP__GAP_50 0x5
#define BV_IR_CTRL_SIR_GAP__GAP_10 0x6
#define BV_IR_CTRL_SIR_GAP__GAP_0 0x7
#define BF_IR_CTRL_SIR_GAP(v) (((v) << 4) & 0x70)
#define BF_IR_CTRL_SIR_GAP_V(v) ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70)
#define BP_IR_CTRL_SIPEN 3
#define BM_IR_CTRL_SIPEN 0x8
#define BF_IR_CTRL_SIPEN(v) (((v) << 3) & 0x8)
#define BP_IR_CTRL_TCEN 2
#define BM_IR_CTRL_TCEN 0x4
#define BF_IR_CTRL_TCEN(v) (((v) << 2) & 0x4)
#define BP_IR_CTRL_TXEN 1
#define BM_IR_CTRL_TXEN 0x2
#define BF_IR_CTRL_TXEN(v) (((v) << 1) & 0x2)
#define BP_IR_CTRL_RXEN 0
#define BM_IR_CTRL_RXEN 0x1
#define BF_IR_CTRL_RXEN(v) (((v) << 0) & 0x1)
/**
* Register: HW_IR_TXDMA
* Address: 0x10
* SCT: yes
*/
#define HW_IR_TXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0))
#define HW_IR_TXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4))
#define HW_IR_TXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8))
#define HW_IR_TXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc))
#define BP_IR_TXDMA_RUN 31
#define BM_IR_TXDMA_RUN 0x80000000
#define BF_IR_TXDMA_RUN(v) (((v) << 31) & 0x80000000)
#define BP_IR_TXDMA_EMPTY 29
#define BM_IR_TXDMA_EMPTY 0x20000000
#define BF_IR_TXDMA_EMPTY(v) (((v) << 29) & 0x20000000)
#define BP_IR_TXDMA_INT 28
#define BM_IR_TXDMA_INT 0x10000000
#define BF_IR_TXDMA_INT(v) (((v) << 28) & 0x10000000)
#define BP_IR_TXDMA_CHANGE 27
#define BM_IR_TXDMA_CHANGE 0x8000000
#define BF_IR_TXDMA_CHANGE(v) (((v) << 27) & 0x8000000)
#define BP_IR_TXDMA_NEW_MTA 24
#define BM_IR_TXDMA_NEW_MTA 0x7000000
#define BF_IR_TXDMA_NEW_MTA(v) (((v) << 24) & 0x7000000)
#define BP_IR_TXDMA_NEW_MODE 22
#define BM_IR_TXDMA_NEW_MODE 0xc00000
#define BF_IR_TXDMA_NEW_MODE(v) (((v) << 22) & 0xc00000)
#define BP_IR_TXDMA_NEW_SPEED 19
#define BM_IR_TXDMA_NEW_SPEED 0x380000
#define BF_IR_TXDMA_NEW_SPEED(v) (((v) << 19) & 0x380000)
#define BP_IR_TXDMA_BOF_TYPE 18
#define BM_IR_TXDMA_BOF_TYPE 0x40000
#define BF_IR_TXDMA_BOF_TYPE(v) (((v) << 18) & 0x40000)
#define BP_IR_TXDMA_XBOFS 12
#define BM_IR_TXDMA_XBOFS 0x3f000
#define BF_IR_TXDMA_XBOFS(v) (((v) << 12) & 0x3f000)
#define BP_IR_TXDMA_XFER_COUNT 0
#define BM_IR_TXDMA_XFER_COUNT 0xfff
#define BF_IR_TXDMA_XFER_COUNT(v) (((v) << 0) & 0xfff)
/**
* Register: HW_IR_RXDMA
* Address: 0x20
* SCT: yes
*/
#define HW_IR_RXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0))
#define HW_IR_RXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4))
#define HW_IR_RXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8))
#define HW_IR_RXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc))
#define BP_IR_RXDMA_RUN 31
#define BM_IR_RXDMA_RUN 0x80000000
#define BF_IR_RXDMA_RUN(v) (((v) << 31) & 0x80000000)
#define BP_IR_RXDMA_XFER_COUNT 0
#define BM_IR_RXDMA_XFER_COUNT 0x3ff
#define BF_IR_RXDMA_XFER_COUNT(v) (((v) << 0) & 0x3ff)
/**
* Register: HW_IR_DBGCTRL
* Address: 0x30
* SCT: yes
*/
#define HW_IR_DBGCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0))
#define HW_IR_DBGCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4))
#define HW_IR_DBGCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8))
#define HW_IR_DBGCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc))
#define BP_IR_DBGCTRL_VFIRSWZ 12
#define BM_IR_DBGCTRL_VFIRSWZ 0x1000
#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0
#define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1
#define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) << 12) & 0x1000)
#define BF_IR_DBGCTRL_VFIRSWZ_V(v) ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000)
#define BP_IR_DBGCTRL_RXFRMOFF 11
#define BM_IR_DBGCTRL_RXFRMOFF 0x800
#define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) << 11) & 0x800)
#define BP_IR_DBGCTRL_RXCRCOFF 10
#define BM_IR_DBGCTRL_RXCRCOFF 0x400
#define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) << 10) & 0x400)
#define BP_IR_DBGCTRL_RXINVERT 9
#define BM_IR_DBGCTRL_RXINVERT 0x200
#define BF_IR_DBGCTRL_RXINVERT(v) (((v) << 9) & 0x200)
#define BP_IR_DBGCTRL_TXFRMOFF 8
#define BM_IR_DBGCTRL_TXFRMOFF 0x100
#define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) << 8) & 0x100)
#define BP_IR_DBGCTRL_TXCRCOFF 7
#define BM_IR_DBGCTRL_TXCRCOFF 0x80
#define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) << 7) & 0x80)
#define BP_IR_DBGCTRL_TXINVERT 6
#define BM_IR_DBGCTRL_TXINVERT 0x40
#define BF_IR_DBGCTRL_TXINVERT(v) (((v) << 6) & 0x40)
#define BP_IR_DBGCTRL_INTLOOPBACK 5
#define BM_IR_DBGCTRL_INTLOOPBACK 0x20
#define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) << 5) & 0x20)
#define BP_IR_DBGCTRL_DUPLEX 4
#define BM_IR_DBGCTRL_DUPLEX 0x10
#define BF_IR_DBGCTRL_DUPLEX(v) (((v) << 4) & 0x10)
#define BP_IR_DBGCTRL_MIO_RX 3
#define BM_IR_DBGCTRL_MIO_RX 0x8
#define BF_IR_DBGCTRL_MIO_RX(v) (((v) << 3) & 0x8)
#define BP_IR_DBGCTRL_MIO_TX 2
#define BM_IR_DBGCTRL_MIO_TX 0x4
#define BF_IR_DBGCTRL_MIO_TX(v) (((v) << 2) & 0x4)
#define BP_IR_DBGCTRL_MIO_SCLK 1
#define BM_IR_DBGCTRL_MIO_SCLK 0x2
#define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) << 1) & 0x2)
#define BP_IR_DBGCTRL_MIO_EN 0
#define BM_IR_DBGCTRL_MIO_EN 0x1
#define BF_IR_DBGCTRL_MIO_EN(v) (((v) << 0) & 0x1)
/**
* Register: HW_IR_INTR
* Address: 0x40
* SCT: yes
*/
#define HW_IR_INTR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0))
#define HW_IR_INTR_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4))
#define HW_IR_INTR_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8))
#define HW_IR_INTR_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc))
#define BP_IR_INTR_RXABORT_IRQ_EN 22
#define BM_IR_INTR_RXABORT_IRQ_EN 0x400000
#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) << 22) & 0x400000)
#define BF_IR_INTR_RXABORT_IRQ_EN_V(v) ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000)
#define BP_IR_INTR_SPEED_IRQ_EN 21
#define BM_IR_INTR_SPEED_IRQ_EN 0x200000
#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) << 21) & 0x200000)
#define BF_IR_INTR_SPEED_IRQ_EN_V(v) ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000)
#define BP_IR_INTR_RXOF_IRQ_EN 20
#define BM_IR_INTR_RXOF_IRQ_EN 0x100000
#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) << 20) & 0x100000)
#define BF_IR_INTR_RXOF_IRQ_EN_V(v) ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000)
#define BP_IR_INTR_TXUF_IRQ_EN 19
#define BM_IR_INTR_TXUF_IRQ_EN 0x80000
#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) << 19) & 0x80000)
#define BF_IR_INTR_TXUF_IRQ_EN_V(v) ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000)
#define BP_IR_INTR_TC_IRQ_EN 18
#define BM_IR_INTR_TC_IRQ_EN 0x40000
#define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_TC_IRQ_EN(v) (((v) << 18) & 0x40000)
#define BF_IR_INTR_TC_IRQ_EN_V(v) ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000)
#define BP_IR_INTR_RX_IRQ_EN 17
#define BM_IR_INTR_RX_IRQ_EN 0x20000
#define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_RX_IRQ_EN(v) (((v) << 17) & 0x20000)
#define BF_IR_INTR_RX_IRQ_EN_V(v) ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000)
#define BP_IR_INTR_TX_IRQ_EN 16
#define BM_IR_INTR_TX_IRQ_EN 0x10000
#define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0
#define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1
#define BF_IR_INTR_TX_IRQ_EN(v) (((v) << 16) & 0x10000)
#define BF_IR_INTR_TX_IRQ_EN_V(v) ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000)
#define BP_IR_INTR_RXABORT_IRQ 6
#define BM_IR_INTR_RXABORT_IRQ 0x40
#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1
#define BF_IR_INTR_RXABORT_IRQ(v) (((v) << 6) & 0x40)
#define BF_IR_INTR_RXABORT_IRQ_V(v) ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40)
#define BP_IR_INTR_SPEED_IRQ 5
#define BM_IR_INTR_SPEED_IRQ 0x20
#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1
#define BF_IR_INTR_SPEED_IRQ(v) (((v) << 5) & 0x20)
#define BF_IR_INTR_SPEED_IRQ_V(v) ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20)
#define BP_IR_INTR_RXOF_IRQ 4
#define BM_IR_INTR_RXOF_IRQ 0x10
#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1
#define BF_IR_INTR_RXOF_IRQ(v) (((v) << 4) & 0x10)
#define BF_IR_INTR_RXOF_IRQ_V(v) ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10)
#define BP_IR_INTR_TXUF_IRQ 3
#define BM_IR_INTR_TXUF_IRQ 0x8
#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1
#define BF_IR_INTR_TXUF_IRQ(v) (((v) << 3) & 0x8)
#define BF_IR_INTR_TXUF_IRQ_V(v) ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8)
#define BP_IR_INTR_TC_IRQ 2
#define BM_IR_INTR_TC_IRQ 0x4
#define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_TC_IRQ__REQUEST 0x1
#define BF_IR_INTR_TC_IRQ(v) (((v) << 2) & 0x4)
#define BF_IR_INTR_TC_IRQ_V(v) ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4)
#define BP_IR_INTR_RX_IRQ 1
#define BM_IR_INTR_RX_IRQ 0x2
#define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_RX_IRQ__REQUEST 0x1
#define BF_IR_INTR_RX_IRQ(v) (((v) << 1) & 0x2)
#define BF_IR_INTR_RX_IRQ_V(v) ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2)
#define BP_IR_INTR_TX_IRQ 0
#define BM_IR_INTR_TX_IRQ 0x1
#define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0
#define BV_IR_INTR_TX_IRQ__REQUEST 0x1
#define BF_IR_INTR_TX_IRQ(v) (((v) << 0) & 0x1)
#define BF_IR_INTR_TX_IRQ_V(v) ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1)
/**
* Register: HW_IR_DATA
* Address: 0x50
* SCT: no
*/
#define HW_IR_DATA (*(volatile unsigned long *)(REGS_IR_BASE + 0x50))
#define BP_IR_DATA_DATA 0
#define BM_IR_DATA_DATA 0xffffffff
#define BF_IR_DATA_DATA(v) (((v) << 0) & 0xffffffff)
/**
* Register: HW_IR_STAT
* Address: 0x60
* SCT: no
*/
#define HW_IR_STAT (*(volatile unsigned long *)(REGS_IR_BASE + 0x60))
#define BP_IR_STAT_PRESENT 31
#define BM_IR_STAT_PRESENT 0x80000000
#define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0
#define BV_IR_STAT_PRESENT__AVAILABLE 0x1
#define BF_IR_STAT_PRESENT(v) (((v) << 31) & 0x80000000)
#define BF_IR_STAT_PRESENT_V(v) ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000)
#define BP_IR_STAT_MODE_ALLOWED 29
#define BM_IR_STAT_MODE_ALLOWED 0x60000000
#define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0
#define BV_IR_STAT_MODE_ALLOWED__FIR 0x1
#define BV_IR_STAT_MODE_ALLOWED__MIR 0x2
#define BV_IR_STAT_MODE_ALLOWED__SIR 0x3
#define BF_IR_STAT_MODE_ALLOWED(v) (((v) << 29) & 0x60000000)
#define BF_IR_STAT_MODE_ALLOWED_V(v) ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000)
#define BP_IR_STAT_ANY_IRQ 28
#define BM_IR_STAT_ANY_IRQ 0x10000000
#define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0
#define BV_IR_STAT_ANY_IRQ__REQUEST 0x1
#define BF_IR_STAT_ANY_IRQ(v) (((v) << 28) & 0x10000000)
#define BF_IR_STAT_ANY_IRQ_V(v) ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000)
#define BP_IR_STAT_RXABORT_SUMMARY 22
#define BM_IR_STAT_RXABORT_SUMMARY 0x400000
#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) << 22) & 0x400000)
#define BF_IR_STAT_RXABORT_SUMMARY_V(v) ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000)
#define BP_IR_STAT_SPEED_SUMMARY 21
#define BM_IR_STAT_SPEED_SUMMARY 0x200000
#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_SPEED_SUMMARY(v) (((v) << 21) & 0x200000)
#define BF_IR_STAT_SPEED_SUMMARY_V(v) ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000)
#define BP_IR_STAT_RXOF_SUMMARY 20
#define BM_IR_STAT_RXOF_SUMMARY 0x100000
#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_RXOF_SUMMARY(v) (((v) << 20) & 0x100000)
#define BF_IR_STAT_RXOF_SUMMARY_V(v) ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000)
#define BP_IR_STAT_TXUF_SUMMARY 19
#define BM_IR_STAT_TXUF_SUMMARY 0x80000
#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_TXUF_SUMMARY(v) (((v) << 19) & 0x80000)
#define BF_IR_STAT_TXUF_SUMMARY_V(v) ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000)
#define BP_IR_STAT_TC_SUMMARY 18
#define BM_IR_STAT_TC_SUMMARY 0x40000
#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_TC_SUMMARY(v) (((v) << 18) & 0x40000)
#define BF_IR_STAT_TC_SUMMARY_V(v) ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000)
#define BP_IR_STAT_RX_SUMMARY 17
#define BM_IR_STAT_RX_SUMMARY 0x20000
#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_RX_SUMMARY(v) (((v) << 17) & 0x20000)
#define BF_IR_STAT_RX_SUMMARY_V(v) ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000)
#define BP_IR_STAT_TX_SUMMARY 16
#define BM_IR_STAT_TX_SUMMARY 0x10000
#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0
#define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1
#define BF_IR_STAT_TX_SUMMARY(v) (((v) << 16) & 0x10000)
#define BF_IR_STAT_TX_SUMMARY_V(v) ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000)
#define BP_IR_STAT_MEDIA_BUSY 2
#define BM_IR_STAT_MEDIA_BUSY 0x4
#define BF_IR_STAT_MEDIA_BUSY(v) (((v) << 2) & 0x4)
#define BP_IR_STAT_RX_ACTIVE 1
#define BM_IR_STAT_RX_ACTIVE 0x2
#define BF_IR_STAT_RX_ACTIVE(v) (((v) << 1) & 0x2)
#define BP_IR_STAT_TX_ACTIVE 0
#define BM_IR_STAT_TX_ACTIVE 0x1
#define BF_IR_STAT_TX_ACTIVE(v) (((v) << 0) & 0x1)
/**
* Register: HW_IR_TCCTRL
* Address: 0x70
* SCT: yes
*/
#define HW_IR_TCCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0))
#define HW_IR_TCCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4))
#define HW_IR_TCCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8))
#define HW_IR_TCCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc))
#define BP_IR_TCCTRL_INIT 31
#define BM_IR_TCCTRL_INIT 0x80000000
#define BF_IR_TCCTRL_INIT(v) (((v) << 31) & 0x80000000)
#define BP_IR_TCCTRL_GO 30
#define BM_IR_TCCTRL_GO 0x40000000
#define BF_IR_TCCTRL_GO(v) (((v) << 30) & 0x40000000)
#define BP_IR_TCCTRL_BUSY 29
#define BM_IR_TCCTRL_BUSY 0x20000000
#define BF_IR_TCCTRL_BUSY(v) (((v) << 29) & 0x20000000)
#define BP_IR_TCCTRL_TEMIC 24
#define BM_IR_TCCTRL_TEMIC 0x1000000
#define BV_IR_TCCTRL_TEMIC__LOW 0x0
#define BV_IR_TCCTRL_TEMIC__HIGH 0x1
#define BF_IR_TCCTRL_TEMIC(v) (((v) << 24) & 0x1000000)
#define BF_IR_TCCTRL_TEMIC_V(v) ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000)
#define BP_IR_TCCTRL_EXT_DATA 16
#define BM_IR_TCCTRL_EXT_DATA 0xff0000
#define BF_IR_TCCTRL_EXT_DATA(v) (((v) << 16) & 0xff0000)
#define BP_IR_TCCTRL_DATA 8
#define BM_IR_TCCTRL_DATA 0xff00
#define BF_IR_TCCTRL_DATA(v) (((v) << 8) & 0xff00)
#define BP_IR_TCCTRL_ADDR 5
#define BM_IR_TCCTRL_ADDR 0xe0
#define BF_IR_TCCTRL_ADDR(v) (((v) << 5) & 0xe0)
#define BP_IR_TCCTRL_INDX 1
#define BM_IR_TCCTRL_INDX 0x1e
#define BF_IR_TCCTRL_INDX(v) (((v) << 1) & 0x1e)
#define BP_IR_TCCTRL_C 0
#define BM_IR_TCCTRL_C 0x1
#define BF_IR_TCCTRL_C(v) (((v) << 0) & 0x1)
/**
* Register: HW_IR_SI_READ
* Address: 0x80
* SCT: no
*/
#define HW_IR_SI_READ (*(volatile unsigned long *)(REGS_IR_BASE + 0x80))
#define BP_IR_SI_READ_ABORT 8
#define BM_IR_SI_READ_ABORT 0x100
#define BF_IR_SI_READ_ABORT(v) (((v) << 8) & 0x100)
#define BP_IR_SI_READ_DATA 0
#define BM_IR_SI_READ_DATA 0xff
#define BF_IR_SI_READ_DATA(v) (((v) << 0) & 0xff)
/**
* Register: HW_IR_DEBUG
* Address: 0x90
* SCT: no
*/
#define HW_IR_DEBUG (*(volatile unsigned long *)(REGS_IR_BASE + 0x90))
#define BP_IR_DEBUG_TXDMAKICK 5
#define BM_IR_DEBUG_TXDMAKICK 0x20
#define BF_IR_DEBUG_TXDMAKICK(v) (((v) << 5) & 0x20)
#define BP_IR_DEBUG_RXDMAKICK 4
#define BM_IR_DEBUG_RXDMAKICK 0x10
#define BF_IR_DEBUG_RXDMAKICK(v) (((v) << 4) & 0x10)
#define BP_IR_DEBUG_TXDMAEND 3
#define BM_IR_DEBUG_TXDMAEND 0x8
#define BF_IR_DEBUG_TXDMAEND(v) (((v) << 3) & 0x8)
#define BP_IR_DEBUG_RXDMAEND 2
#define BM_IR_DEBUG_RXDMAEND 0x4
#define BF_IR_DEBUG_RXDMAEND(v) (((v) << 2) & 0x4)
#define BP_IR_DEBUG_TXDMAREQ 1
#define BM_IR_DEBUG_TXDMAREQ 0x2
#define BF_IR_DEBUG_TXDMAREQ(v) (((v) << 1) & 0x2)
#define BP_IR_DEBUG_RXDMAREQ 0
#define BM_IR_DEBUG_RXDMAREQ 0x1
#define BF_IR_DEBUG_RXDMAREQ(v) (((v) << 0) & 0x1)
#endif /* __HEADERGEN__STMP3600__IR__H__ */
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