2012-11-14 11:51:51 +00:00
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.section .text,"ax",%progbits
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.code 32
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.align 0x04
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.global start
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start:
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2013-08-11 17:17:36 +00:00
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sub r7, pc, #8 /* Copy running address */
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2012-11-14 11:51:51 +00:00
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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2013-10-21 22:23:33 +00:00
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#ifdef CONFIG_STMP
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2013-08-11 17:17:36 +00:00
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/* Disable MMU, disable caching and buffering;
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* use low exception range address */
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =0x3005
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bic r0, r1
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mcr p15, 0, r0, c1, c0, 0
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2013-10-21 22:23:33 +00:00
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#endif
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2012-11-14 11:51:51 +00:00
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ldr sp, =oc_stackend
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2013-08-11 17:17:36 +00:00
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/* Relocate to right address */
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mov r2, r7
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ldr r3, =_copystart
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ldr r4, =_copyend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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mov r2, #0
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mcr p15, 0, r2, c7, c5, 0 @ Invalidate ICache
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/* Jump to real location */
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ldr pc, =remap
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remap:
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2012-11-14 11:51:51 +00:00
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/* clear bss */
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ldr r2, =bss_start
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ldr r3, =bss_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* jump to C code */
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b main
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