2006-03-02 13:28:24 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Marcoen Hirschberg
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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2007-07-05 07:14:24 +00:00
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#ifndef __S3C2440_H__
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#define __S3C2440_H__
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2006-03-02 13:28:24 +00:00
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2008-04-22 04:34:25 +00:00
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#define LCD_BUFFER_SIZE (320*240*2)
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#define TTB_SIZE (0x4000)
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/* must be 16Kb (0x4000) aligned */
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#define TTB_BASE ((unsigned int *)(0x30000000 + (32*1024*1024) - TTB_SIZE)) /* End of memory */
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#define FRAME ((short *) ((char *)TTB_BASE - LCD_BUFFER_SIZE)) /* Right before TTB */
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2006-03-02 13:28:24 +00:00
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/* Memory Controllers */
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#define BWSCON (*(volatile int *)0x48000000) /* Bus width & wait status control */
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#define BANKCON0 (*(volatile int *)0x48000004) /* Boot ROM control */
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#define BANKCON1 (*(volatile int *)0x48000008) /* BANK1 control */
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#define BANKCON2 (*(volatile int *)0x4800000C) /* BANK2 control */
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#define BANKCON3 (*(volatile int *)0x48000010) /* BANK3 control */
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#define BANKCON4 (*(volatile int *)0x48000014) /* BANK4 control */
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#define BANKCON5 (*(volatile int *)0x48000018) /* BANK5 control */
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#define BANKCON6 (*(volatile int *)0x4800001C) /* BANK6 control */
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#define BANKCON7 (*(volatile int *)0x48000020) /* BANK7 control */
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#define REFRESH (*(volatile int *)0x48000024) /* DRAM/SDRAM refresh control */
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#define BANKSIZE (*(volatile int *)0x48000028) /* Flexible bank size */
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#define MRSRB6 (*(volatile int *)0x4800002C) /* Mode register set for SDRAM BANK6 */
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#define MRSRB7 (*(volatile int *)0x48000030) /* Mode register set for SDRAM BANK7 */
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/* USB Host Controller */
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/* Control and status group */
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#define HcRevision (*(volatile int *)0x49000000)
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#define HcControl (*(volatile int *)0x49000004)
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#define HcCommonStatus (*(volatile int *)0x49000008)
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#define HcInterruptStatus (*(volatile int *)0x4900000C)
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#define HcInterruptEnable (*(volatile int *)0x49000010)
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#define HcInterruptDisable (*(volatile int *)0x49000014)
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/* Memory pointer group */
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#define HcHCCA (*(volatile int *)0x49000018)
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#define HcPeriodCuttentED (*(volatile int *)0x4900001C)
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#define HcControlHeadED (*(volatile int *)0x49000020)
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#define HcControlCurrentED (*(volatile int *)0x49000024)
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#define HcBulkHeadED (*(volatile int *)0x49000028)
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#define HcBulkCurrentED (*(volatile int *)0x4900002C)
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/* Frame counter group */
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#define HcDoneHead (*(volatile int *)0x49000030)
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#define HcRmInterval (*(volatile int *)0x49000034)
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#define HcFmRemaining (*(volatile int *)0x49000038)
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#define HcFmNumber (*(volatile int *)0x4900003C)
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#define HcPeriodicStart (*(volatile int *)0x49000040)
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#define HcLSThreshold (*(volatile int *)0x49000044)
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/* Root hub group */
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#define HcRhDescriptorA (*(volatile int *)0x49000048)
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#define HcRhDescriptorB (*(volatile int *)0x4900004C)
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#define HcRhStatus (*(volatile int *)0x49000050)
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#define HcRhPortStatus1 (*(volatile int *)0x49000054)
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#define HcRhPortStatus2 (*(volatile int *)0x49000058)
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/* Interrupt Controller */
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#define SRCPND (*(volatile int *)0x4A000000) /* Interrupt request status */
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#define INTMOD (*(volatile int *)0x4A000004) /* Interrupt mode control */
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#define INTMSK (*(volatile int *)0x4A000008) /* Interrupt mask control */
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#define PRIORITY (*(volatile int *)0x4A00000C) /* IRQ priority control */
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#define INTPND (*(volatile int *)0x4A000010) /* Interrupt request status */
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#define INTOFFSET (*(volatile int *)0x4A000014) /* Interrupt request source offset */
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#define SUBSRCPND (*(volatile int *)0x4A000018) /* Sub source pending */
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#define INTSUBMSK (*(volatile int *)0x4A00001C) /* Interrupt sub mask */
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2007-07-05 07:14:24 +00:00
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/* Interrupt indexes - INTOFFSET - IRQ mode only */
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/* Arbiter 5 => Arbiter 6 Req 5 */
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2007-07-05 08:21:10 +00:00
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#define ADC_INTOFFSET 31 /* REQ4 */
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#define RTC_INTOFFSET 30 /* REQ3 */
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#define SPI1_INTOFFSET 29 /* REQ2 */
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#define UART0_INTOFFSET 28 /* REQ1 */
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2007-07-05 07:14:24 +00:00
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/* Arbiter 4 => Arbiter 6 Req 4 */
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2007-07-05 08:21:10 +00:00
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#define IIC_INTOFFSET 27 /* REQ5 */
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#define USBH_INTOFFSET 26 /* REQ4 */
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#define USBD_INTOFFSET 25 /* REQ3 */
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#define NFCON_INTOFFSET 24 /* REQ2 */
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#define UART1_INTOFFSET 23 /* REQ1 */
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#define SPI0_INTOFFSET 22 /* REQ0 */
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2007-07-05 07:14:24 +00:00
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/* Arbiter 3 => Arbiter 6 Req 3 */
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2007-07-05 08:21:10 +00:00
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#define SDI_INTOFFSET 21 /* REQ5 */
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#define DMA3_INTOFFSET 20 /* REQ4 */
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#define DMA2_INTOFFSET 19 /* REQ3 */
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#define DMA1_INTOFFSET 18 /* REQ2 */
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#define DMA0_INTOFFSET 17 /* REQ1 */
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#define LCD_INTOFFSET 16 /* REQ0 */
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2007-07-05 07:14:24 +00:00
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/* Arbiter 2 => Arbiter 6 Req 2 */
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2007-07-05 08:21:10 +00:00
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#define UART2_INTOFFSET 15 /* REQ5 */
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#define TIMER4_INTOFFSET 14 /* REQ4 */
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#define TIMER3_INTOFFSET 13 /* REQ3 */
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#define TIMER2_INTOFFSET 12 /* REQ2 */
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#define TIMER1_INTOFFSET 11 /* REQ1 */
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#define TIMER0_INTOFFSET 10 /* REQ0 */
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2007-07-05 07:14:24 +00:00
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/* Arbiter 1 => Arbiter 6 Req 1 */
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2007-07-05 08:21:10 +00:00
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#define WDT_AC97_INTOFFSET 9 /* REQ5 */
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#define TICK_INTOFFSET 8 /* REQ4 */
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#define nBATT_FLT_INTOFFSET 7 /* REQ3 */
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#define CAM_INTOFFSET 6 /* REQ2 */
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#define EINT8_23_INTOFFSET 5 /* REQ1 */
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#define EINT4_7_INTOFFSET 4 /* REQ0 */
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2007-07-05 07:14:24 +00:00
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/* Arbiter 0 => Arbiter 6 Req 0 */
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2007-07-05 08:21:10 +00:00
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#define EINT3_INTOFFSET 3 /* REQ4 */
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#define EINT2_INTOFFSET 2 /* REQ3 */
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#define EINT1_INTOFFSET 1 /* REQ2 */
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#define EINT0_INTOFFSET 0 /* REQ1 */
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2007-07-05 07:14:24 +00:00
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/* Interrupt bitmasks - SRCPND, INTMOD, INTMSK, INTPND */
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/* Arbiter 5 => Arbiter 6 Req 5 */
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#define ADC_MASK (1 << 31) /* REQ4 */
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#define RTC_MASK (1 << 30) /* REQ3 */
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#define SPI1_MASK (1 << 29) /* REQ2 */
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#define UART0_MASK (1 << 28) /* REQ1 */
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/* Arbiter 4 => Arbiter 6 Req 4 */
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#define IIC_MASK (1 << 27) /* REQ5 */
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#define USBH_MASK (1 << 26) /* REQ4 */
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#define USBD_MASK (1 << 25) /* REQ3 */
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#define NFCON_MASK (1 << 24) /* REQ2 */
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#define UART1_MASK (1 << 23) /* REQ1 */
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#define SPI0_MASK (1 << 22) /* REQ0 */
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/* Arbiter 3 => Arbiter 6 Req 3 */
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#define SDI_MASK (1 << 21) /* REQ5 */
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#define DMA3_MASK (1 << 20) /* REQ4 */
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#define DMA2_MASK (1 << 19) /* REQ3 */
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#define DMA1_MASK (1 << 18) /* REQ2 */
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#define DMA0_MASK (1 << 17) /* REQ1 */
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#define LCD_MASK (1 << 16) /* REQ0 */
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/* Arbiter 2 => Arbiter 6 Req 2 */
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#define UART2_MASK (1 << 15) /* REQ5 */
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#define TIMER4_MASK (1 << 14) /* REQ4 */
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#define TIMER3_MASK (1 << 13) /* REQ3 */
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#define TIMER2_MASK (1 << 12) /* REQ2 */
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#define TIMER1_MASK (1 << 11) /* REQ1 */
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#define TIMER0_MASK (1 << 10) /* REQ0 */
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/* Arbiter 1 => Arbiter 6 Req 1 */
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#define WDT_AC97_MASK (1 << 9) /* REQ5 */
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#define TICK_MASK (1 << 8) /* REQ4 */
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#define nBATT_FLT_MASK (1 << 7) /* REQ3 */
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#define CAM_MASK (1 << 6) /* REQ2 */
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#define EINT8_23_MASK (1 << 5) /* REQ1 */
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#define EINT4_7_MASK (1 << 4) /* REQ0 */
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/* Arbiter 0 => Arbiter 6 Req 0 */
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#define EINT3_MASK (1 << 3) /* REQ4 */
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#define EINT2_MASK (1 << 2) /* REQ3 */
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#define EINT1_MASK (1 << 1) /* REQ2 */
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#define EINT0_MASK (1 << 0) /* REQ1 */
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2006-03-02 13:28:24 +00:00
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/* DMA */
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#define DISRC0 (*(volatile int *)0x4B000000) /* DMA 0 initial source */
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#define DISRCC0 (*(volatile int *)0x4B000004) /* DMA 0 initial source control */
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#define DIDST0 (*(volatile int *)0x4B000008) /* DMA 0 initial destination */
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#define DIDSTC0 (*(volatile int *)0x4B00000C) /* DMA 0 initial destination control */
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#define DCON0 (*(volatile int *)0x4B000010) /* DMA 0 control */
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#define DSTAT0 (*(volatile int *)0x4B000014) /* DMA 0 count */
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#define DCSRC0 (*(volatile int *)0x4B000018) /* DMA 0 current source */
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#define DCDST0 (*(volatile int *)0x4B00001C) /* DMA 0 current destination */
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#define DMASKTRIG0 (*(volatile int *)0x4B000020) /* DMA 0 mask trigger */
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#define DISRC1 (*(volatile int *)0x4B000040) /* DMA 1 initial source */
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#define DISRCC1 (*(volatile int *)0x4B000044) /* DMA 1 initial source control */
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#define DIDST1 (*(volatile int *)0x4B000048) /* DMA 1 initial destination */
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#define DIDSTC1 (*(volatile int *)0x4B00004C) /* DMA 1 initial destination control */
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#define DCON1 (*(volatile int *)0x4B000050) /* DMA 1 control */
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#define DSTAT1 (*(volatile int *)0x4B000054) /* DMA 1 count */
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#define DCSRC1 (*(volatile int *)0x4B000058) /* DMA 1 current source */
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#define DCDST1 (*(volatile int *)0x4B00005C) /* DMA 1 current destination */
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#define DMASKTRIG1 (*(volatile int *)0x4B000060) /* DMA 1 mask trigger */
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#define DISRC2 (*(volatile int *)0x4B000080) /* DMA 2 initial source */
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#define DISRCC2 (*(volatile int *)0x4B000084) /* DMA 2 initial source control */
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#define DIDST2 (*(volatile int *)0x4B000088) /* DMA 2 initial destination */
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#define DIDSTC2 (*(volatile int *)0x4B00008C) /* DMA 2 initial destination control */
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#define DCON2 (*(volatile int *)0x4B000090) /* DMA 2 control */
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#define DSTAT2 (*(volatile int *)0x4B000094) /* DMA 2 count */
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#define DCSRC2 (*(volatile int *)0x4B000098) /* DMA 2 current source */
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#define DCDST2 (*(volatile int *)0x4B00009C) /* DMA 2 current destination */
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#define DMASKTRIG2 (*(volatile int *)0x4B0000A0) /* DMA 2 mask trigger */
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#define DISRC3 (*(volatile int *)0x4B0000C0) /* DMA 3 initial source */
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#define DISRCC3 (*(volatile int *)0x4B0000C4) /* DMA 3 initial source control */
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#define DIDST3 (*(volatile int *)0x4B0000C8) /* DMA 3 initial destination */
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#define DIDSTC3 (*(volatile int *)0x4B0000CC) /* DMA 3 initial destination control */
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#define DCON3 (*(volatile int *)0x4B0000D0) /* DMA 3 control */
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#define DSTAT3 (*(volatile int *)0x4B0000D4) /* DMA 3 count */
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#define DCSRC3 (*(volatile int *)0x4B0000D8) /* DMA 3 current source */
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#define DCDST3 (*(volatile int *)0x4B0000DC) /* DMA 3 current destination */
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#define DMASKTRIG3 (*(volatile int *)0x4B0000E0) /* DMA 3 mask trigger */
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/* Clock & Power Management */
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#define LOCKTIME (*(volatile int *)0x4C000000) /* PLL lock time counter */
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#define MPLLCON (*(volatile int *)0x4C000004) /* MPLL control */
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#define UPLLCON (*(volatile int *)0x4C000008) /* UPLL control */
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#define CLKCON (*(volatile int *)0x4C00000C) /* Clock generator control */
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#define CLKSLOW (*(volatile int *)0x4C000010) /* Slow clock control */
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#define CLKDIVN (*(volatile int *)0x4C000014) /* Clock divider control */
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#define CAMDIVN (*(volatile int *)0x4C000018) /* Camera clock divider control */
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/* LCD Controller */
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#define LCDCON1 (*(volatile int *)0x4D000000) /* LCD control 1 */
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#define LCDCON2 (*(volatile int *)0x4D000004) /* LCD control 2 */
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#define LCDCON3 (*(volatile int *)0x4D000008) /* LCD control 3 */
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#define LCDCON4 (*(volatile int *)0x4D00000C) /* LCD control 4 */
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#define LCDCON5 (*(volatile int *)0x4D000010) /* LCD control 5 */
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#define LCDSADDR1 (*(volatile int *)0x4D000014) /* STN/TFT: frame buffer start address 1 */
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#define LCDSADDR2 (*(volatile int *)0x4D000018) /* STN/TFT: frame buffer start address 2 */
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#define LCDSADDR3 (*(volatile int *)0x4D00001C) /* STN/TFT: virtual screen address set */
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#define REDLUT (*(volatile int *)0x4D000020) /* STN: red lookup table */
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#define GREENLUT (*(volatile int *)0x4D000024) /* STN: green lookup table */
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#define BLUELUT (*(volatile int *)0x4D000028) /* STN: blue lookup table */
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#define DITHMODE (*(volatile int *)0x4D00004C) /* STN: dithering mode */
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#define TPAL (*(volatile int *)0x4D000050) /* TFT: temporary palette */
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#define LCDINTPND (*(volatile int *)0x4D000054) /* LCD interrupt pending */
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#define LCDSRCPND (*(volatile int *)0x4D000058) /* LCD interrupt source */
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#define LCDINTMSK (*(volatile int *)0x4D00005C) /* LCD interrupt mask */
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#define TCONSEL (*(volatile int *)0x4D000060) /* TCON(LPC3600/LCC3600) control */
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/* NAND Flash */
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#define NFCONF (*(volatile int *)0x4E000000) /* NAND flash configuration */
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#define NFCONT (*(volatile int *)0x4E000004) /* NAND flash control */
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#define NFCMD (*(volatile int *)0x4E000008) /* NAND flash command */
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#define NFADDR (*(volatile int *)0x4E00000C) /* NAND flash address */
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#define NFDATA (*(volatile int *)0x4E000010) /* NAND flash data */
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#define NFMECC0 (*(volatile int *)0x4E000014) /* NAND flash main area ECC0/1 */
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#define NFMECC1 (*(volatile int *)0x4E000018) /* NAND flash main area ECC2/3 */
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#define NFSECC (*(volatile int *)0x4E00001C) /* NAND flash spare area ECC */
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#define NFSTAT (*(volatile int *)0x4E000020) /* NAND flash operation status */
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#define NFESTAT0 (*(volatile int *)0x4E000024) /* NAND flash ECC status for I/O[7:0] */
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#define NFESTAT1 (*(volatile int *)0x4E000028) /* NAND flash ECC status for I/O[15:8] */
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#define NFMECCSTAT0 (*(volatile int *)0x4E00002C) /* NAND flash main area ECC0 status */
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#define NFMECCSTAT1 (*(volatile int *)0x4E000030) /* NAND flash main area ECC1 status */
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#define NFSECCSTAT (*(volatile int *)0x4E000034) /* NAND flash spare area ECC status */
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#define NFSBLK (*(volatile int *)0x4E000038) /* NAND flash start block address */
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#define NFEBLK (*(volatile int *)0x4E00003C) /* NAND flash end block address */
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/* Camera Interface */
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#define CISRCFMT (*(volatile int *)0x4F000000) /* Input source format */
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#define CIWDOFST (*(volatile int *)0x4F000004) /* Window offset register */
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#define CIGCTRL (*(volatile int *)0x4F000008) /* Global control register */
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#define CICOYSA1 (*(volatile int *)0x4F000018) /* Y 1st frame start address for codec DMA */
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#define CICOYSA2 (*(volatile int *)0x4F00001C) /* Y 2nd frame start address for codec DMA */
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#define CICOYSA3 (*(volatile int *)0x4F000020) /* Y 3nd frame start address for codec DMA */
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#define CICOYSA4 (*(volatile int *)0x4F000024) /* Y 4th frame start address for codec DMA */
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#define CICOCBSA1 (*(volatile int *)0x4F000028) /* Cb 1st frame start address for codec DMA */
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#define CICOCBSA2 (*(volatile int *)0x4F00002C) /* Cb 2nd frame start address for codec DMA */
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#define CICOCBSA3 (*(volatile int *)0x4F000030) /* Cb 3nd frame start address for codec DMA */
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#define CICOCBSA4 (*(volatile int *)0x4F000034) /* Cb 4th frame start address for codec DMA */
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#define CICOCRSA1 (*(volatile int *)0x4F000038) /* Cr 1st frame start address for codec DMA */
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#define CICOCRSA2 (*(volatile int *)0x4F00003C) /* Cr 2nd frame start address for codec DMA */
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#define CICOCRSA3 (*(volatile int *)0x4F000040) /* Cr 3nd frame start address for codec DMA */
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#define CICOCRSA4 (*(volatile int *)0x4F000044) /* Cr 4th frame start address for codec DMA */
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#define CICOTRGFMT (*(volatile int *)0x4F000048) /* Target image format of codec DMA */
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#define CICOCTRL (*(volatile int *)0x4F00004C
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/* Codec DMA control related */
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#define CICOSCPRERATIO (*(volatile int *)0x4F000050) /* Codec pre-scaler ratio control */
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#define CICOSCPREDST (*(volatile int *)0x4F000054) /* Codec pre-scaler destination format */
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#define CICOSCCTRL (*(volatile int *)0x4F000058) /* Codec main-scaler control */
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#define CICOTAREA (*(volatile int *)0x4F00005C) /* Codec scaler target area */
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#define CICOSTATUS (*(volatile int *)0x4F000064) /* Codec path status */
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#define CIPRCLRSA1 (*(volatile int *)0x4F00006C) /* RGB 1st frame start address for preview DMA */
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#define CIPRCLRSA2 (*(volatile int *)0x4F000070) /* RGB 2nd frame start address for preview DMA */
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#define CIPRCLRSA3 (*(volatile int *)0x4F000074) /* RGB 3nd frame start address for preview DMA */
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#define CIPRCLRSA4 (*(volatile int *)0x4F000078) /* RGB 4th frame start address for preview DMA */
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#define CIPRTRGFMT (*(volatile int *)0x4F00007C) /* Target image format of preview DMA */
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#define CIPRCTRL (*(volatile int *)0x4F000080) /* Preview DMA control related */
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#define CIPRSCPRERATIO (*(volatile int *)0x4F000084) /* Preview pre-scaler ratio control */
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#define CIPRSCPREDST (*(volatile int *)0x4F000088) /* Preview pre-scaler destination format */
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#define CIPRSCCTRL (*(volatile int *)0x4F00008C) /* Preview main-scaler control */
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#define CIPRTAREA (*(volatile int *)0x4F000090) /* Preview scaler target area */
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#define CIPRSTATUS (*(volatile int *)0x4F000098) /* Preview path status */
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#define CIIMGCPT (*(volatile int *)0x4F0000A0) /* Image capture enable command */
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/* UART */
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#define ULCON0 (*(volatile int *)0x50000000) /* UART 0 line control */
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#define UCON0 (*(volatile int *)0x50000004) /* UART 0 control */
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#define UFCON0 (*(volatile int *)0x50000008) /* UART 0 FIFO control */
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#define UMCON0 (*(volatile int *)0x5000000C) /* UART 0 modem control */
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#define UTRSTAT0 (*(volatile int *)0x50000010) /* UART 0 Tx/Rx status */
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#define UERSTAT0 (*(volatile int *)0x50000014) /* UART 0 Rx error status */
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#define UFSTAT0 (*(volatile int *)0x50000018) /* UART 0 FIFO status */
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#define UMSTAT0 (*(volatile int *)0x5000001C) /* UART 0 modem status */
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#define UTXH0 (*(volatile char *)0x50000020) /* UART 0 transmission hold */
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#define URXH0 (*(volatile char *)0x50000024) /* UART 0 receive buffer */
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#define UBRDIV0 (*(volatile int *)0x50000028) /* UART 0 baud rate divisor */
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#define ULCON1 (*(volatile int *)0x50004000) /* UART 1 line control */
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#define UCON1 (*(volatile int *)0x50004004) /* UART 1 control */
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#define UFCON1 (*(volatile int *)0x50004008) /* UART 1 FIFO control */
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#define UMCON1 (*(volatile int *)0x5000400C) /* UART 1 modem control */
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#define UTRSTAT1 (*(volatile int *)0x50004010) /* UART 1 Tx/Rx status */
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#define UERSTAT1 (*(volatile int *)0x50004014) /* UART 1 Rx error status */
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#define UFSTAT1 (*(volatile int *)0x50004018) /* UART 1 FIFO status */
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#define UMSTAT1 (*(volatile int *)0x5000401C) /* UART 1 modem status */
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#define UTXH1 (*(volatile char*)0x50004020) /* UART 1 transmission hold */
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#define URXH1 (*(volatile char*)0x50004024) /* UART 1 receive buffer */
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#define UBRDIV1 (*(volatile int *)0x50004028) /* UART 1 baud rate divisor */
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#define ULCON2 (*(volatile int *)0x50008000) /* UART 2 line control */
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#define UCON2 (*(volatile int *)0x50008004) /* UART 2 control */
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#define UFCON2 (*(volatile int *)0x50008008) /* UART 2 FIFO control */
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#define UTRSTAT2 (*(volatile int *)0x50008010) /* UART 2 Tx/Rx status */
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#define UERSTAT2 (*(volatile int *)0x50008014) /* UART 2 Rx error status */
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#define UFSTAT2 (*(volatile int *)0x50008018) /* UART 2 FIFO status */
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#define UTXH2 (*(volatile char*)0x50008020) /* UART 2 transmission hold */
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#define URXH2 (*(volatile char*)0x50008024) /* UART 2 receive buffer */
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#define UBRDIV2 (*(volatile int *)0x50008028) /* UART 2 baud rate divisor */
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/* PWM Timer */
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#define TCFG0 (*(volatile int *)0x51000000) /* Timer configuration */
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#define TCFG1 (*(volatile int *)0x51000004) /* Timer configuration */
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#define TCON (*(volatile int *)0x51000008) /* Timer control */
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#define TCNTB0 (*(volatile int *)0x5100000C) /* Timer count buffer 0 */
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#define TCMPB0 (*(volatile int *)0x51000010) /* Timer compare buffer 0 */
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#define TCNTO0 (*(volatile int *)0x51000014) /* Timer count observation 0 */
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#define TCNTB1 (*(volatile int *)0x51000018) /* Timer count buffer 1 */
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#define TCMPB1 (*(volatile int *)0x5100001C) /* Timer compare buffer 1 */
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#define TCNTO1 (*(volatile int *)0x51000020) /* Timer count observation 1 */
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#define TCNTB2 (*(volatile int *)0x51000024) /* Timer count buffer 2 */
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#define TCMPB2 (*(volatile int *)0x51000028) /* Timer compare buffer 2 */
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#define TCNTO2 (*(volatile int *)0x5100002C) /* Timer count observation 2 */
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#define TCNTB3 (*(volatile int *)0x51000030) /* Timer count buffer 3 */
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#define TCMPB3 (*(volatile int *)0x51000034) /* Timer compare buffer 3 */
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#define TCNTO3 (*(volatile int *)0x51000038) /* Timer count observation 3 */
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#define TCNTB4 (*(volatile int *)0x5100003C) /* Timer count buffer 4 */
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#define TCNTO4 (*(volatile int *)0x51000040) /* Timer count observation 4 */
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/* USB Device */
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#define FUNC_ADDR_REG (*(volatile char *)0x52000140) /* Function address */
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#define PWR_REG (*(volatile char *)0x52000144) /* Power management */
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#define EP_INT_REG (*(volatile char *)0x52000148) /* EP interrupt pending and clear */
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#define USB_INT_REG (*(volatile char *)0x52000158) /* USB interrupt pending and clear */
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#define EP_INT_EN_REG (*(volatile char *)0x5200015C) /* Interrupt enable */
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#define USB_INT_EN_REG (*(volatile char *)0x5200016C) /* Interrupt enable */
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#define FRAME_NUM1_REG (*(volatile char *)0x52000170) /* Frame number lower byte */
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#define FRAME_NUM2_REG (*(volatile char *)0x52000174) /* Frame number higher byte */
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#define INDEX_REG (*(volatile char *)0x52000178) /* Register index */
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#define EP0_CSR (*(volatile char *)0x52000184) /* Endpoint 0 status */
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#define IN_CSR1_REG (*(volatile char *)0x52000184) /* In endpoint control status */
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#define IN_CSR2_REG (*(volatile char *)0x52000188) /* In endpoint control status */
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#define MAXP_REG (*(volatile char *)0x52000180) /* Endpoint max packet */
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#define OUT_CSR1_REG (*(volatile char *)0x52000190) /* Out endpoint control status */
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#define OUT_CSR2_REG (*(volatile char *)0x52000194) /* Out endpoint control status */
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#define OUT_FIFO_CNT1_REG (*(volatile char *)0x52000198) /* Endpoint out write count */
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#define OUT_FIFO_CNT2_REG (*(volatile char *)0x5200019C) /* Endpoint out write count */
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#define EP0_FIFO (*(volatile char *)0x520001C0) /* Endpoint 0 FIFO */
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#define EP1_FIFO (*(volatile char *)0x520001C4) /* Endpoint 1 FIFO */
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#define EP2_FIFO (*(volatile char *)0x520001C8) /* Endpoint 2 FIFO */
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#define EP3_FIFO (*(volatile char *)0x520001CC) /* Endpoint 3 FIFO */
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#define EP4_FIFO (*(volatile char *)0x520001D0) /* Endpoint 4 FIFO */
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#define EP1_DMA_CON (*(volatile char *)0x52000200) /* EP1 DMA Interface control */
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#define EP1_DMA_UNIT (*(volatile char *)0x52000204) /* EP1 DMA Tx unit counter */
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#define EP1_DMA_FIFO (*(volatile char *)0x52000208) /* EP1 DMA Tx FIFO counter */
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#define EP1_DMA_TTC_L (*(volatile char *)0x5200020C) /* EP1 DMA Total Tx counter */
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#define EP1_DMA_TTC_M (*(volatile char *)0x52000210) /* EP1 DMA Total Tx counter */
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#define EP1_DMA_TTC_H (*(volatile char *)0x52000214) /* EP1 DMA Total Tx counter */
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#define EP2_DMA_CON (*(volatile char *)0x52000218) /* EP2 DMA interface control */
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#define EP2_DMA_UNIT (*(volatile char *)0x5200021C) /* EP2 DMA Tx Unit counter */
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#define EP2_DMA_FIFO (*(volatile char *)0x52000220) /* EP2 DMA Tx FIFO counter */
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#define EP2_DMA_TTC_L (*(volatile char *)0x52000224) /* EP2 DMA total Tx counter */
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#define EP2_DMA_TTC_M (*(volatile char *)0x52000228) /* EP2 DMA total Tx counter */
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#define EP2_DMA_TTC_H (*(volatile char *)0x5200022C) /* EP2 DMA Total Tx counter */
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#define EP3_DMA_CON (*(volatile char *)0x52000240) /* EP3 DMA Interface control */
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#define EP3_DMA_UNIT (*(volatile char *)0x52000244) /* EP3 DMA Tx Unit counter */
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#define EP3_DMA_FIFO (*(volatile char *)0x52000248) /* EP3 DMA Tx FIFO counter */
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#define EP3_DMA_TTC_L (*(volatile char *)0x5200024C) /* EP3 DMA Total Tx counter */
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#define EP3_DMA_TTC_M (*(volatile char *)0x52000250) /* EP3 DMA Total Tx counter */
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#define EP3_DMA_TTC_H (*(volatile char *)0x52000254) /* EP3 DMA Total Tx counter */
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#define EP4_DMA_CON (*(volatile char *)0x52000258) /* EP4 DMA Interface control */
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#define EP4_DMA_UNIT (*(volatile char *)0x5200025C) /* EP4 DMA Tx Unit counter */
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#define EP4_DMA_FIFO (*(volatile char *)0x52000260) /* EP4 DMA Tx FIFO counter */
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#define EP4_DMA_TTC_L (*(volatile char *)0x52000264) /* EP4 DMA Total Tx counter */
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#define EP4_DMA_TTC_M (*(volatile char *)0x52000268) /* EP4 DMA Total Tx counter */
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#define EP4_DMA_TTC_H (*(volatile char *)0x5200026C) /* EP4 DMA Total Tx counter */
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/* Watchdog Timer */
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#define WTCON (*(volatile int *)0x53000000) /* Watchdog timer mode */
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#define WTDAT (*(volatile int *)0x53000004) /* Watchdog timer data */
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#define WTCNT (*(volatile int *)0x53000008) /* Watchdog timer count */
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/* IIC */
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#define IICCON (*(volatile int *)0x54000000) /* IIC control */
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#define IICSTAT (*(volatile int *)0x54000004) /* IIC status */
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#define IICADD (*(volatile int *)0x54000008) /* IIC address */
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#define IICDS (*(volatile int *)0x5400000C) /* IIC data shift */
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#define IICLC (*(volatile int *)0x54000010) /* IIC multi-master line control */
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/* IIS */
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#define IISCON (*(volatile int *)0x55000000) /* IIS control */
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#define IISMOD (*(volatile int *)0x55000004) /* IIS mode */
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#define IISPSR (*(volatile int *)0x55000008) /* IIS prescaler */
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#define IISFCON (*(volatile int *)0x5500000C) /* IIS FIFO control */
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#define IISFIFO (*(volatile short *)0x55000010) /* IIS FIFO entry */
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/* I/O port */
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#define GPACON (*(volatile int *)0x56000000) /* Port A control */
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#define GPADAT (*(volatile int *)0x56000004) /* Port A data */
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#define GPBCON (*(volatile int *)0x56000010) /* Port B control */
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#define GPBDAT (*(volatile int *)0x56000014) /* Port B data */
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#define GPBUP (*(volatile int *)0x56000018) /* Pull-up control B */
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#define GPCCON (*(volatile int *)0x56000020) /* Port C control */
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#define GPCDAT (*(volatile int *)0x56000024) /* Port C data */
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#define GPCUP (*(volatile int *)0x56000028) /* Pull-up control C */
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#define GPDCON (*(volatile int *)0x56000030) /* Port D control */
|
2006-11-05 07:55:00 +00:00
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#define GPDDAT (*(volatile int *)0x56000034) /* Port D data */
|
2006-03-02 13:28:24 +00:00
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#define GPDUP (*(volatile int *)0x56000038) /* Pull-up control D */
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#define GPECON (*(volatile int *)0x56000040) /* Port E control */
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#define GPEDAT (*(volatile int *)0x56000044) /* Port E data */
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#define GPEUP (*(volatile int *)0x56000048) /* Pull-up control E */
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#define GPFCON (*(volatile int *)0x56000050) /* Port F control */
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#define GPFDAT (*(volatile int *)0x56000054) /* Port F data */
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#define GPFUP (*(volatile int *)0x56000058) /* Pull-up control F */
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#define GPGCON (*(volatile int *)0x56000060) /* Port G control */
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#define GPGDAT (*(volatile int *)0x56000064) /* Port G data */
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#define GPGUP (*(volatile int *)0x56000068) /* Pull-up control G */
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#define GPHCON (*(volatile int *)0x56000070) /* Port H control */
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#define GPHDAT (*(volatile int *)0x56000074) /* Port H data */
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#define GPHUP (*(volatile int *)0x56000078) /* Pull-up control H */
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#define MISCCR (*(volatile int *)0x56000080) /* Miscellaneous control */
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#define DCLKCON (*(volatile int *)0x56000084) /* DCLK0/1 control */
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#define EXTINT0 (*(volatile int *)0x56000088) /* External interrupt control register 0 */
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#define EXTINT1 (*(volatile int *)0x5600008C) /* External interrupt control register 1 */
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#define EXTINT2 (*(volatile int *)0x56000090) /* External interrupt control register 2 */
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#define EINTFLT0 (*(volatile int *)0x56000094) /* Reserved */
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#define EINTFLT1 (*(volatile int *)0x56000098) /* Reserved */
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#define EINTFLT2 (*(volatile int *)0x5600009C) /* External interrupt filter control register 2 */
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#define EINTFLT3 (*(volatile int *)0x560000A0) /* External interrupt filter control register 3 */
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#define EINTMASK (*(volatile int *)0x560000A4) /* External interrupt mask */
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#define EINTPEND (*(volatile int *)0x560000A8) /* External interrupt pending */
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#define GSTATUS0 (*(volatile int *)0x560000AC) /* External pin status */
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#define GSTATUS1 (*(volatile int *)0x560000B0) /* Chip ID */
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#define GSTATUS2 (*(volatile int *)0x560000B4) /* Reset status */
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#define GSTATUS3 (*(volatile int *)0x560000B8) /* Inform register */
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#define GSTATUS4 (*(volatile int *)0x560000BC) /* Inform register */
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#define MSLCON (*(volatile int *)0x560000CC) /* Memory sleep control register */
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#define GPJCON (*(volatile int *)0x560000D0) /* Port J control */
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#define GPJDAT (*(volatile int *)0x560000D4) /* Port J data */
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#define GPJUP (*(volatile int *)0x560000D8) /* Pull-up control J */
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/* RTC */
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#define RTCCON (*(volatile char *)0x57000040) /* RTC control */
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#define TICNT (*(volatile char *)0x57000044) /* Tick time count */
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#define RTCALM (*(volatile char *)0x57000050) /* RTC alarm control */
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#define ALMSEC (*(volatile char *)0x57000054) /* Alarm second */
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#define ALMMIN (*(volatile char *)0x57000058) /* Alarm minute */
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#define ALMHOUR (*(volatile char *)0x5700005C) /* Alarm hour */
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#define ALMDATE (*(volatile char *)0x57000060) /* alarm day */
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#define ALMMON (*(volatile char *)0x57000064) /* Alarm month */
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#define ALMYEAR (*(volatile char *)0x57000068) /* Alarm year */
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#define BCDSEC (*(volatile char *)0x57000070) /* BCD second */
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#define BCDMIN (*(volatile char *)0x57000074) /* BCD minute */
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#define BCDHOUR (*(volatile char *)0x57000078) /* BCD hour */
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#define BCDDATE (*(volatile char *)0x5700007C) /* BCD day */
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#define BCDDAY (*(volatile char *)0x57000080) /* BCD date */
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#define BCDMON (*(volatile char *)0x57000084) /* BCD month */
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#define BCDYEAR (*(volatile char *)0x57000088) /* BCD year */
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/* A/D Converter */
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#define ADCCON (*(volatile int *)0x58000000) /* ADC control */
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#define ADCTSC (*(volatile int *)0x58000004) /* ADC touch screen control */
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#define ADCDLY (*(volatile int *)0x58000008) /* ADC start or interval delay */
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#define ADCDAT0 (*(volatile int *)0x5800000C) /* ADC conversion data */
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#define ADCDAT1 (*(volatile int *)0x58000010) /* ADC conversion data */
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#define ADCUPDN (*(volatile int *)0x58000014) /* Stylus up or down interrupt status */
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/* SPI */
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#define SPCON0 (*(volatile int *)0x59000000) /* SPI control */
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#define SPSTA0 (*(volatile int *)0x59000004) /* SPI status */
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#define SPPIN0 (*(volatile int *)0x59000008) /* SPI pin control */
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#define SPPRE0 (*(volatile int *)0x5900000C) /* SPI baud rate prescaler */
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#define SPTDAT0 (*(volatile int *)0x59000010) /* SPI Tx data */
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#define SPRDAT0 (*(volatile int *)0x59000014) /* SPI Rx data */
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#define SPCON1 (*(volatile int *)0x59000020) /* SPI control */
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#define SPSTA1 (*(volatile int *)0x59000024) /* SPI status */
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#define SPPIN1 (*(volatile int *)0x59000028) /* SPI pin control */
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#define SPPRE1 (*(volatile int *)0x5900002C) /* SPI baud rate prescaler */
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#define SPTDAT1 (*(volatile int *)0x59000030) /* SPI Tx data */
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#define SPRDAT1 (*(volatile int *)0x59000034) /* SPI Rx data */
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/* SD Interface */
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#define SDICON (*(volatile int *)0x5A000000) /* SDI control */
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#define SDIPRE (*(volatile int *)0x5A000004) /* SDI baud rate prescaler */
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#define SDICARG (*(volatile int *)0x5A000008) /* SDI command argument */
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#define SDICCON (*(volatile int *)0x5A00000C) /* SDI command control */
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#define SDICSTA (*(volatile int *)0x5A000010) /* SDI command status */
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#define SDIRSP0 (*(volatile int *)0x5A000014) /* SDI response */
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#define SDIRSP1 (*(volatile int *)0x5A000018) /* SDI response */
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#define SDIRSP2 (*(volatile int *)0x5A00001C) /* SDI response */
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#define SDIRSP3 (*(volatile int *)0x5A000020) /* SDI response */
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#define SDIDTIMER (*(volatile int *)0x5A000024) /* SDI data / busy timer */
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#define SDIBSIZE (*(volatile int *)0x5A000028) /* SDI block size */
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#define SDIDCON (*(volatile int *)0x5A00002C) /* SDI data control */
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#define SDIDCNT (*(volatile int *)0x5A000030) /* SDI data remain counter */
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#define SDIDSTA (*(volatile int *)0x5A000034) /* SDI data status */
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#define SDIFSTA (*(volatile int *)0x5A000038) /* SDI FIFO status */
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#define SDIIMSK (*(volatile int *)0x5A00003C) /* SDI interrupt mask */
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#define SDIDAT (*(volatile char *)0x5A000040) /* SDI data */
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/* AC97 Audio-CODEC Interface */
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#define AC_GLBCTRL (*(volatile int *)0x5B000000) /* AC97 global control register */
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#define AC_GLBSTAT (*(volatile int *)0x5B000004) /* AC97 global status register */
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#define AC_CODEC_CMD (*(volatile int *)0x5B000008) /* AC97 codec command register */
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#define AC_CODEC_STAT (*(volatile int *)0x5B00000C) /* AC97 codec status register */
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#define AC_PCMADDR (*(volatile int *)0x5B000010) /* AC97 PCM out/in channel FIFO address register */
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#define AC_MICADDR (*(volatile int *)0x5B000014) /* AC97 mic in channel FIFO address register */
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#define AC_PCMDATA (*(volatile int *)0x5B000018) /* AC97 PCM out/in channel FIFO data register */
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#define AC_MICDATA (*(volatile int *)0x5B00001C) /* AC97 MIC in channel FIFO data register */
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/* Memory banks */
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#define BANK0 0x00000000
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#define BANK1 0x08000000
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#define BANK2 0x10000000
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#define BANK3 0x18000000
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#define BANK4 0x20000000
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#define BANK5 0x28000000
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#define DRAM0 0x30000000
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#define DRAM1 0x31000000
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#define BOOTRAM 0x40000000
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2007-07-05 07:14:24 +00:00
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#endif /* __S3C2440_H__ */
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