269 lines
7.8 KiB
C
269 lines
7.8 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: system-s5l8700.c 28935 2010-12-30 20:23:46Z Buschel $
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*
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* Copyright (C) 2007 by Rob Purchase
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "system-target.h"
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#include "pmu-target.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked, \
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weak, alias("fiq_dummy")));
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default_interrupt(INT_IRQ0);
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default_interrupt(INT_IRQ1);
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default_interrupt(INT_IRQ2);
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default_interrupt(INT_IRQ3);
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default_interrupt(INT_IRQ4);
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default_interrupt(INT_IRQ5);
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default_interrupt(INT_IRQ6);
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default_interrupt(INT_IRQ7);
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default_interrupt(INT_TIMERA);
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default_interrupt(INT_TIMERB);
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default_interrupt(INT_TIMERC);
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default_interrupt(INT_TIMERD);
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default_interrupt(INT_TIMERE);
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default_interrupt(INT_TIMERF);
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default_interrupt(INT_TIMERG);
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default_interrupt(INT_TIMERH);
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default_interrupt(INT_IRQ9);
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default_interrupt(INT_IRQ10);
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default_interrupt(INT_IRQ11);
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default_interrupt(INT_IRQ12);
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default_interrupt(INT_IRQ13);
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default_interrupt(INT_IRQ14);
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default_interrupt(INT_IRQ15);
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default_interrupt(INT_DMAC0C0);
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default_interrupt(INT_DMAC0C1);
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default_interrupt(INT_DMAC0C2);
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default_interrupt(INT_DMAC0C3);
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default_interrupt(INT_DMAC0C4);
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default_interrupt(INT_DMAC0C5);
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default_interrupt(INT_DMAC0C6);
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default_interrupt(INT_DMAC0C7);
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default_interrupt(INT_DMAC1C0);
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default_interrupt(INT_DMAC1C1);
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default_interrupt(INT_DMAC1C2);
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default_interrupt(INT_DMAC1C3);
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default_interrupt(INT_DMAC1C4);
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default_interrupt(INT_DMAC1C5);
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default_interrupt(INT_DMAC1C6);
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default_interrupt(INT_DMAC1C7);
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default_interrupt(INT_IRQ18);
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default_interrupt(INT_USB_FUNC);
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default_interrupt(INT_IRQ20);
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default_interrupt(INT_IRQ21);
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default_interrupt(INT_IRQ22);
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default_interrupt(INT_WHEEL);
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default_interrupt(INT_IRQ24);
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default_interrupt(INT_IRQ25);
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default_interrupt(INT_IRQ26);
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default_interrupt(INT_IRQ27);
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default_interrupt(INT_IRQ28);
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default_interrupt(INT_ATA);
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default_interrupt(INT_IRQ30);
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default_interrupt(INT_IRQ31);
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default_interrupt(INT_IRQ32);
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default_interrupt(INT_IRQ33);
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default_interrupt(INT_IRQ34);
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default_interrupt(INT_IRQ35);
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default_interrupt(INT_IRQ36);
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default_interrupt(INT_IRQ37);
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default_interrupt(INT_IRQ38);
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default_interrupt(INT_IRQ39);
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default_interrupt(INT_IRQ40);
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default_interrupt(INT_IRQ41);
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default_interrupt(INT_IRQ42);
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default_interrupt(INT_IRQ43);
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default_interrupt(INT_IRQ44);
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default_interrupt(INT_IRQ45);
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default_interrupt(INT_IRQ46);
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default_interrupt(INT_IRQ47);
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default_interrupt(INT_IRQ48);
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default_interrupt(INT_IRQ49);
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default_interrupt(INT_IRQ50);
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default_interrupt(INT_IRQ51);
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default_interrupt(INT_IRQ52);
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default_interrupt(INT_IRQ53);
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default_interrupt(INT_IRQ54);
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default_interrupt(INT_IRQ55);
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default_interrupt(INT_IRQ56);
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default_interrupt(INT_IRQ57);
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default_interrupt(INT_IRQ58);
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default_interrupt(INT_IRQ59);
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default_interrupt(INT_IRQ60);
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default_interrupt(INT_IRQ61);
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default_interrupt(INT_IRQ62);
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default_interrupt(INT_IRQ63);
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int current_irq;
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void INT_TIMER(void) ICODE_ATTR;
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void INT_TIMER()
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{
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if (TACON & (TACON >> 4) & 0x7000) INT_TIMERA();
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if (TBCON & (TBCON >> 4) & 0x7000) INT_TIMERB();
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if (TCCON & (TCCON >> 4) & 0x7000) INT_TIMERC();
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if (TDCON & (TDCON >> 4) & 0x7000) INT_TIMERD();
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if (TFCON & (TFCON >> 4) & 0x7000) INT_TIMERF();
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if (TGCON & (TGCON >> 4) & 0x7000) INT_TIMERG();
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if (THCON & (THCON >> 4) & 0x7000) INT_TIMERH();
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}
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void INT_DMAC0(void) ICODE_ATTR;
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void INT_DMAC0()
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{
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uint32_t intsts = DMAC0INTSTS;
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if (intsts & 1) INT_DMAC0C0();
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if (intsts & 2) INT_DMAC0C1();
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if (intsts & 4) INT_DMAC0C2();
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if (intsts & 8) INT_DMAC0C3();
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if (intsts & 0x10) INT_DMAC0C4();
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if (intsts & 0x20) INT_DMAC0C5();
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if (intsts & 0x40) INT_DMAC0C6();
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if (intsts & 0x80) INT_DMAC0C7();
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}
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void INT_DMAC1(void) ICODE_ATTR;
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void INT_DMAC1()
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{
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uint32_t intsts = DMAC1INTSTS;
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if (intsts & 1) INT_DMAC1C0();
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if (intsts & 2) INT_DMAC1C1();
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if (intsts & 4) INT_DMAC1C2();
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if (intsts & 8) INT_DMAC1C3();
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if (intsts & 0x10) INT_DMAC1C4();
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if (intsts & 0x20) INT_DMAC1C5();
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if (intsts & 0x40) INT_DMAC1C6();
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if (intsts & 0x80) INT_DMAC1C7();
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}
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static void (* const irqvector[])(void) =
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{
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INT_IRQ0,INT_IRQ1,INT_IRQ2,INT_IRQ3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_IRQ7,
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INT_TIMER,INT_IRQ9,INT_IRQ10,INT_IRQ11,INT_IRQ12,INT_IRQ13,INT_IRQ14,INT_IRQ15,
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INT_DMAC0,INT_DMAC1,INT_IRQ18,INT_USB_FUNC,INT_IRQ20,INT_IRQ21,INT_IRQ22,INT_WHEEL,
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INT_IRQ24,INT_IRQ25,INT_IRQ26,INT_IRQ27,INT_IRQ28,INT_ATA,INT_IRQ30,INT_IRQ31,
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INT_IRQ32,INT_IRQ33,INT_IRQ34,INT_IRQ35,INT_IRQ36,INT_IRQ37,INT_IRQ38,INT_IRQ39,
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INT_IRQ40,INT_IRQ41,INT_IRQ42,INT_IRQ43,INT_IRQ55,INT_IRQ56,INT_IRQ57,INT_IRQ58,
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INT_IRQ48,INT_IRQ49,INT_IRQ50,INT_IRQ51,INT_IRQ52,INT_IRQ53,INT_IRQ54,INT_IRQ55,
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INT_IRQ56,INT_IRQ57,INT_IRQ58,INT_IRQ59,INT_IRQ60,INT_IRQ61,INT_IRQ62,INT_IRQ63
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};
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static void UIRQ(void)
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{
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panicf("Unhandled IRQ %d!", current_irq);
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}
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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void* dummy = VIC0ADDRESS;
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dummy = VIC1ADDRESS;
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uint32_t irqs0 = VIC0IRQSTATUS;
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uint32_t irqs1 = VIC1IRQSTATUS;
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for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1)
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if (irqs0 & 1)
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irqvector[current_irq]();
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for (current_irq = 32; irqs1; current_irq++, irqs1 >>= 1)
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if (irqs1 & 1)
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irqvector[current_irq]();
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VIC0ADDRESS = NULL;
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VIC1ADDRESS = NULL;
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_dummy(void)
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{
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asm volatile (
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"subs pc, lr, #4 \r\n"
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);
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}
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void system_init(void)
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{
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pmu_init();
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VIC0INTENABLE = 1 << IRQ_WHEEL;
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}
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void system_reboot(void)
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{
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/* Reset the SoC */
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asm volatile("msr CPSR_c, #0xd3 \n"
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"mov r0, #0x100000 \n"
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"mov r1, #0x3c800000 \n"
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"str r0, [r1] \n");
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/* Wait for reboot to kick in */
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while(1);
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}
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//extern void post_mortem_stub(void);
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void system_exception_wait(void)
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{
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// post_mortem_stub();
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while(1);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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if (cpu_frequency == frequency)
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return;
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if (frequency == CPUFREQ_MAX)
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{
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//TODO: Figure out and implement
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}
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else
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{
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//TODO: Figure out and implement
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}
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cpu_frequency = frequency;
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}
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#endif
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