2011-02-27 22:47:55 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 Dave Chapman
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "thread.h"
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#include "disk.h"
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#include "storage.h"
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#include "timer.h"
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#include "kernel.h"
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#include "string.h"
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#include "power.h"
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#include "panic.h"
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#include "mmu-arm.h"
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#include "mmcdefs-target.h"
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#include "s5l8702.h"
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#include "led.h"
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#include "ata_idle_notify.h"
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Rewrite filesystem code (WIP)
This patch redoes the filesystem code from the FAT driver up to the
clipboard code in onplay.c.
Not every aspect of this is finished therefore it is still "WIP". I
don't wish to do too much at once (haha!). What is left to do is get
dircache back in the sim and find an implementation for the dircache
indicies in the tagcache and playlist code or do something else that
has the same benefit. Leaving these out for now does not make anything
unusable. All the basics are done.
Phone app code should probably get vetted (and app path handling
just plain rewritten as environment expansions); the SDL app and
Android run well.
Main things addressed:
1) Thread safety: There is none right now in the trunk code. Most of
what currently works is luck when multiple threads are involved or
multiple descriptors to the same file are open.
2) POSIX compliance: Many of the functions behave nothing like their
counterparts on a host system. This leads to inconsistent code or very
different behavior from native to hosted. One huge offender was
rename(). Going point by point would fill a book.
3) Actual running RAM usage: Many targets will use less RAM and less
stack space (some more RAM because I upped the number of cache buffers
for large memory). There's very little memory lying fallow in rarely-used
areas (see 'Key core changes' below). Also, all targets may open the same
number of directory streams whereas before those with less than 8MB RAM
were limited to 8, not 12 implying those targets will save slightly
less.
4) Performance: The test_disk plugin shows markedly improved performance,
particularly in the area of (uncached) directory scanning, due partly to
more optimal directory reading and to a better sector cache algorithm.
Uncached times tend to be better while there is a bit of a slowdown in
dircache due to it being a bit heavier of an implementation. It's not
noticeable by a human as far as I can say.
Key core changes:
1) Files and directories share core code and data structures.
2) The filesystem code knows which descriptors refer to same file.
This ensures that changes from one stream are appropriately reflected
in every open descriptor for that file (fileobj_mgr.c).
3) File and directory cache buffers are borrowed from the main sector
cache. This means that when they are not in use by a file, they are not
wasted, but used for the cache. Most of the time, only a few of them
are needed. It also means that adding more file and directory handles
is less expensive. All one must do in ensure a large enough cache to
borrow from.
4) Relative path components are supported and the namespace is unified.
It does not support full relative paths to an implied current directory;
what is does support is use of "." and "..". Adding the former would
not be very difficult. The namespace is unified in the sense that
volumes may be specified several times along with relative parts, e.g.:
"/<0>/foo/../../<1>/bar" :<=> "/<1>/bar".
5) Stack usage is down due to sharing of data, static allocation and
less duplication of strings on the stack. This requires more
serialization than I would like but since the number of threads is
limited to a low number, the tradoff in favor of the stack seems
reasonable.
6) Separates and heirarchicalizes (sic) the SIM and APP filesystem
code. SIM path and volume handling is just like the target. Some
aspects of the APP file code get more straightforward (e.g. no path
hashing is needed).
Dircache:
Deserves its own section. Dircache is new but pays homage to the old.
The old one was not compatible and so it, since it got redone, does
all the stuff it always should have done such as:
1) It may be update and used at any time during the build process.
No longer has one to wait for it to finish building to do basic file
management (create, remove, rename, etc.).
2) It does not need to be either fully scanned or completely disabled;
it can be incomplete (i.e. overfilled, missing paths), still be
of benefit and be correct.
3) Handles mounting and dismounting of individual volumes which means
a full rebuild is not needed just because you pop a new SD card in the
slot. Now, because it reuses its freed entry data, may rebuild only
that volume.
4) Much more fundamental to the file code. When it is built, it is
the keeper of the master file list whether enabled or not ("disabled"
is just a state of the cache). Its must always to ready to be started
and bind all streams opened prior to being enabled.
5) Maintains any short filenames in OEM format which means that it does
not need to be rebuilt when changing the default codepage.
Miscellaneous Compatibility:
1) Update any other code that would otherwise not work such as the
hotswap mounting code in various card drivers.
2) File management: Clipboard needed updating because of the behavioral
changes. Still needs a little more work on some finer points.
3) Remove now-obsolete functionality such as the mutex's "no preempt"
flag (which was only for the prior FAT driver).
4) struct dirinfo uses time_t rather than raw FAT directory entry
time fields. I plan to follow up on genericizing everything there
(i.e. no FAT attributes).
5) unicode.c needed some redoing so that the file code does not try
try to load codepages during a scan, which is actually a problem with
the current code. The default codepage, if any is required, is now
kept in RAM separarately (bufalloced) from codepages specified to
iso_decode() (which must not be bufalloced because the conversion
may be done by playback threads).
Brings with it some additional reusable core code:
1) Revised file functions: Reusable code that does things such as
safe path concatenation and parsing without buffer limitations or
data duplication. Variants that copy or alter the input path may be
based off these.
To do:
1) Put dircache functionality back in the sim. Treating it internally
as a different kind of file system seems the best approach at this
time.
2) Restore use of dircache indexes in the playlist and database or
something effectively the same. Since the cache doesn't have to be
complete in order to be used, not getting a hit on the cache doesn't
unambiguously say if the path exists or not.
Change-Id: Ia30f3082a136253e3a0eae0784e3091d138915c8
Reviewed-on: http://gerrit.rockbox.org/566
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested: Michael Sevakis <jethead71@rockbox.org>
2013-08-06 02:02:45 +00:00
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#include "disk_cache.h"
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2011-02-27 22:47:55 +00:00
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#ifndef ATA_RETRIES
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#define ATA_RETRIES 3
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#endif
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#define CEATA_POWERUP_TIMEOUT 20000000
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#define CEATA_COMMAND_TIMEOUT 1000000
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#define CEATA_DAT_NONBUSY_TIMEOUT 5000000
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#define CEATA_MMC_RCA 1
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/** static, private data **/
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2014-11-10 00:50:19 +00:00
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static uint8_t ceata_taskfile[16] STORAGE_ALIGN_ATTR;
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static uint16_t ata_identify_data[0x100] STORAGE_ALIGN_ATTR;
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2011-04-22 21:39:17 +00:00
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static bool ceata;
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static bool ata_lba48;
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static bool ata_dma;
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static uint64_t ata_total_sectors;
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static struct mutex ata_mutex;
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2011-03-02 08:49:38 +00:00
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static struct semaphore ata_wakeup;
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2011-02-27 22:47:55 +00:00
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static uint32_t ata_dma_flags;
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static long ata_last_activity_value = -1;
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static long ata_sleep_timeout = 20 * HZ;
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static uint32_t ata_stack[(DEFAULT_STACK_SIZE + 0x400) / 4];
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static bool ata_powered;
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static const int ata_retries = ATA_RETRIES;
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static const bool ata_error_srst = true;
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2011-03-02 08:49:38 +00:00
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static struct semaphore mmc_wakeup;
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static struct semaphore mmc_comp_wakeup;
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2011-02-27 22:47:55 +00:00
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static int spinup_time = 0;
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static int dma_mode = 0;
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2014-11-10 00:50:19 +00:00
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static char aligned_buffer[SECTOR_SIZE] STORAGE_ALIGN_ATTR;
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2011-02-27 22:47:55 +00:00
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2016-02-14 11:58:36 +00:00
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static int ata_reset(void);
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2011-02-27 22:47:55 +00:00
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static uint16_t ata_read_cbr(uint32_t volatile* reg)
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{
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while (!(ATA_PIO_READY & 2));
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volatile uint32_t dummy __attribute__((unused)) = *reg;
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while (!(ATA_PIO_READY & 1));
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return ATA_PIO_RDATA;
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}
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static void ata_write_cbr(uint32_t volatile* reg, uint16_t data)
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{
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while (!(ATA_PIO_READY & 2));
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*reg = data;
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}
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static int ata_wait_for_not_bsy(long timeout)
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{
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long startusec = USEC_TIMER;
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while (true)
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{
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uint8_t csd = ata_read_cbr(&ATA_PIO_CSD);
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if (!(csd & BIT(7))) return 0;
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if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(0);
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2014-09-18 03:10:31 +00:00
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yield();
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2011-02-27 22:47:55 +00:00
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}
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}
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static int ata_wait_for_rdy(long timeout)
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{
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long startusec = USEC_TIMER;
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PASS_RC(ata_wait_for_not_bsy(timeout), 1, 0);
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while (true)
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{
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uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
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if (dad & BIT(6)) return 0;
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if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(1);
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2014-09-18 03:10:31 +00:00
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yield();
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2011-02-27 22:47:55 +00:00
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}
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}
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static int ata_wait_for_start_of_transfer(long timeout)
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{
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long startusec = USEC_TIMER;
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PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
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while (true)
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{
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uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
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if (dad & BIT(0)) RET_ERR(1);
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if ((dad & (BIT(7) | BIT(3))) == BIT(3)) return 0;
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if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(2);
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2014-09-18 03:10:31 +00:00
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yield();
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2011-02-27 22:47:55 +00:00
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}
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}
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static int ata_wait_for_end_of_transfer(long timeout)
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{
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PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
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uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
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if (dad & BIT(0)) RET_ERR(1);
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if ((dad & (BIT(3) | BITRANGE(5, 7))) == BIT(6)) return 0;
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RET_ERR(2);
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}
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2011-04-22 21:39:17 +00:00
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static int mmc_dsta_check_command_success(bool disable_crc)
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2011-02-27 22:47:55 +00:00
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{
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int rc = 0;
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uint32_t dsta = SDCI_DSTA;
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if (dsta & SDCI_DSTA_RESTOUTE) rc |= 1;
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if (dsta & SDCI_DSTA_RESENDE) rc |= 2;
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if (dsta & SDCI_DSTA_RESINDE) rc |= 4;
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if (!disable_crc)
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if (dsta & SDCI_DSTA_RESCRCE)
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rc |= 8;
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if (rc) RET_ERR(rc);
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return 0;
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}
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2011-04-22 21:39:17 +00:00
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static bool mmc_send_command(uint32_t cmd, uint32_t arg, uint32_t* result, int timeout)
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2011-02-27 22:47:55 +00:00
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{
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long starttime = USEC_TIMER;
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while ((SDCI_STATE & SDCI_STATE_CMD_STATE_MASK) != SDCI_STATE_CMD_STATE_CMD_IDLE)
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{
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if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(0);
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yield();
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}
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SDCI_STAC = SDCI_STAC_CLR_CMDEND | SDCI_STAC_CLR_BIT_3
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| SDCI_STAC_CLR_RESEND | SDCI_STAC_CLR_DATEND
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| SDCI_STAC_CLR_DAT_CRCEND | SDCI_STAC_CLR_CRC_STAEND
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| SDCI_STAC_CLR_RESTOUTE | SDCI_STAC_CLR_RESENDE
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| SDCI_STAC_CLR_RESINDE | SDCI_STAC_CLR_RESCRCE
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| SDCI_STAC_CLR_WR_DATCRCE | SDCI_STAC_CLR_RD_DATCRCE
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| SDCI_STAC_CLR_RD_DATENDE0 | SDCI_STAC_CLR_RD_DATENDE1
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| SDCI_STAC_CLR_RD_DATENDE2 | SDCI_STAC_CLR_RD_DATENDE3
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| SDCI_STAC_CLR_RD_DATENDE4 | SDCI_STAC_CLR_RD_DATENDE5
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| SDCI_STAC_CLR_RD_DATENDE6 | SDCI_STAC_CLR_RD_DATENDE7;
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SDCI_ARGU = arg;
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SDCI_CMD = cmd;
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if (!(SDCI_DSTA & SDCI_DSTA_CMDRDY)) RET_ERR(1);
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SDCI_CMD = cmd | SDCI_CMD_CMDSTR;
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long sleepbase = USEC_TIMER;
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while (TIMEOUT_EXPIRED(sleepbase, 1000)) yield();
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while (!(SDCI_DSTA & SDCI_DSTA_CMDEND))
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{
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if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(2);
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yield();
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}
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if ((cmd & SDCI_CMD_RES_TYPE_MASK) != SDCI_CMD_RES_TYPE_NONE)
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{
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while (!(SDCI_DSTA & SDCI_DSTA_RESEND))
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{
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if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(3);
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yield();
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}
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if (cmd & SDCI_CMD_RES_BUSY)
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while (SDCI_DSTA & SDCI_DSTA_DAT_BUSY)
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{
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if (TIMEOUT_EXPIRED(starttime, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(4);
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yield();
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}
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}
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bool nocrc = (cmd & SDCI_CMD_RES_SIZE_MASK) == SDCI_CMD_RES_SIZE_136;
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PASS_RC(mmc_dsta_check_command_success(nocrc), 3, 5);
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if (result) *result = SDCI_RESP0;
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return 0;
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}
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|
2011-04-22 21:39:17 +00:00
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static int mmc_get_card_status(uint32_t* result)
|
2011-02-27 22:47:55 +00:00
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{
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return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_STATUS)
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|
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| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
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MMC_CMD_SEND_STATUS_RCA(CEATA_MMC_RCA), result, CEATA_COMMAND_TIMEOUT);
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}
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|
2011-04-22 21:39:17 +00:00
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|
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static int mmc_init(void)
|
2011-02-27 22:47:55 +00:00
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{
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sleep(HZ / 10);
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PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_GO_IDLE_STATE)
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| SDCI_CMD_CMD_TYPE_BC | SDCI_CMD_RES_TYPE_NONE
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
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0, NULL, CEATA_COMMAND_TIMEOUT), 3, 0);
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long startusec = USEC_TIMER;
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uint32_t result;
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do
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{
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if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(1);
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sleep(HZ / 100);
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PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_OP_COND)
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|
|
| SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R3
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
|
|
|
|
|
MMC_CMD_SEND_OP_COND_OCR(MMC_OCR_270_360),
|
|
|
|
|
NULL, CEATA_COMMAND_TIMEOUT), 3, 2);
|
|
|
|
|
result = SDCI_RESP0;
|
|
|
|
|
}
|
|
|
|
|
while (!(result & MMC_OCR_POWER_UP_DONE));
|
|
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_ALL_SEND_CID)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R2
|
|
|
|
|
| SDCI_CMD_RES_SIZE_136 | SDCI_CMD_NCR_NID_NID,
|
|
|
|
|
0, NULL, CEATA_COMMAND_TIMEOUT), 3, 3);
|
|
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SET_RELATIVE_ADDR)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R1
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_SET_RELATIVE_ADDR_RCA(CEATA_MMC_RCA),
|
|
|
|
|
NULL, CEATA_COMMAND_TIMEOUT), 3, 4);
|
|
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SELECT_CARD)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_SELECT_CARD_RCA(CEATA_MMC_RCA),
|
|
|
|
|
NULL, CEATA_COMMAND_TIMEOUT), 3, 5);
|
|
|
|
|
PASS_RC(mmc_get_card_status(&result), 3, 6);
|
|
|
|
|
if ((result & MMC_STATUS_CURRENT_STATE_MASK) != MMC_STATUS_CURRENT_STATE_TRAN) RET_ERR(7);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int mmc_fastio_write(uint32_t addr, uint32_t data)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_WRITE
|
|
|
|
|
| MMC_CMD_FAST_IO_ADDRESS(addr) | MMC_CMD_FAST_IO_DATA(data),
|
|
|
|
|
NULL, CEATA_COMMAND_TIMEOUT);
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int mmc_fastio_read(uint32_t addr, uint32_t* data)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_READ
|
|
|
|
|
| MMC_CMD_FAST_IO_ADDRESS(addr), data, CEATA_COMMAND_TIMEOUT);
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_soft_reset(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
PASS_RC(mmc_fastio_write(6, 4), 2, 0);
|
|
|
|
|
sleep(HZ / 100);
|
|
|
|
|
PASS_RC(mmc_fastio_write(6, 0), 2, 1);
|
|
|
|
|
sleep(HZ / 100);
|
|
|
|
|
long startusec = USEC_TIMER;
|
|
|
|
|
uint32_t status;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
PASS_RC(mmc_fastio_read(0xf, &status), 2, 2);
|
|
|
|
|
if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(3);
|
|
|
|
|
sleep(HZ / 100);
|
|
|
|
|
}
|
|
|
|
|
while (status & 0x80);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int mmc_dsta_check_data_success(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
int rc = 0;
|
|
|
|
|
uint32_t dsta = SDCI_DSTA;
|
|
|
|
|
if (dsta & (SDCI_DSTA_WR_DATCRCE | SDCI_DSTA_RD_DATCRCE))
|
|
|
|
|
{
|
|
|
|
|
if (dsta & SDCI_DSTA_WR_DATCRCE) rc |= 1;
|
|
|
|
|
if (dsta & SDCI_DSTA_RD_DATCRCE) rc |= 2;
|
|
|
|
|
if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_TXERR) rc |= 4;
|
|
|
|
|
else if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_CARDERR) rc |= 8;
|
|
|
|
|
}
|
|
|
|
|
if (dsta & (SDCI_DSTA_RD_DATENDE0 | SDCI_DSTA_RD_DATENDE1 | SDCI_DSTA_RD_DATENDE2
|
|
|
|
|
| SDCI_DSTA_RD_DATENDE3 | SDCI_DSTA_RD_DATENDE4 | SDCI_DSTA_RD_DATENDE5
|
|
|
|
|
| SDCI_DSTA_RD_DATENDE6 | SDCI_DSTA_RD_DATENDE7))
|
|
|
|
|
rc |= 16;
|
|
|
|
|
if (rc) RET_ERR(rc);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static void mmc_discard_irq(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
SDCI_IRQ = SDCI_IRQ_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT
|
|
|
|
|
| SDCI_IRQ_MASK_MASK_READ_WAIT_INT;
|
2011-03-02 08:49:38 +00:00
|
|
|
semaphore_wait(&mmc_wakeup, 0);
|
2011-02-27 22:47:55 +00:00
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_read_multiple_register(uint32_t addr, void* dest, uint32_t size)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
if (size > 0x10) RET_ERR(0);
|
|
|
|
|
mmc_discard_irq();
|
|
|
|
|
SDCI_DMASIZE = size;
|
|
|
|
|
SDCI_DMACOUNT = 1;
|
|
|
|
|
SDCI_DMAADDR = dest;
|
|
|
|
|
SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
2011-12-17 07:54:00 +00:00
|
|
|
commit_discard_dcache();
|
2011-02-27 22:47:55 +00:00
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_RES_TYPE_R1
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ
|
|
|
|
|
| MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
|
|
|
|
|
| MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
|
|
|
|
|
NULL, CEATA_COMMAND_TIMEOUT), 2, 1);
|
2011-03-02 08:49:38 +00:00
|
|
|
if (semaphore_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT * HZ / 1000000)
|
|
|
|
|
== OBJ_WAIT_TIMEDOUT) RET_ERR(2);
|
2011-02-27 22:47:55 +00:00
|
|
|
PASS_RC(mmc_dsta_check_data_success(), 2, 3);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
uint32_t i;
|
|
|
|
|
if (size > 0x10) RET_ERR(0);
|
|
|
|
|
mmc_discard_irq();
|
|
|
|
|
SDCI_DMASIZE = size;
|
|
|
|
|
SDCI_DMACOUNT = 0;
|
|
|
|
|
SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
|
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR
|
|
|
|
|
| SDCI_CMD_RES_BUSY | SDCI_CMD_RES_TYPE_R1
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE
|
|
|
|
|
| MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
|
|
|
|
|
| MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
|
|
|
|
|
NULL, CEATA_COMMAND_TIMEOUT), 3, 1);
|
|
|
|
|
SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
|
|
|
|
|
for (i = 0; i < size / 4; i++) SDCI_DATA = ((uint32_t*)dest)[i];
|
|
|
|
|
long startusec = USEC_TIMER;
|
2011-03-02 08:49:38 +00:00
|
|
|
if (semaphore_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT * HZ / 1000000)
|
|
|
|
|
== OBJ_WAIT_TIMEDOUT) RET_ERR(2);
|
2011-02-27 22:47:55 +00:00
|
|
|
while ((SDCI_STATE & SDCI_STATE_DAT_STATE_MASK) != SDCI_STATE_DAT_STATE_IDLE)
|
|
|
|
|
{
|
|
|
|
|
if (TIMEOUT_EXPIRED(startusec, CEATA_COMMAND_TIMEOUT)) RET_ERR(3);
|
|
|
|
|
yield();
|
|
|
|
|
}
|
|
|
|
|
PASS_RC(mmc_dsta_check_data_success(), 3, 4);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_init(int buswidth)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
uint32_t result;
|
|
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
|
|
|
|
|
| MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_HS_TIMING)
|
|
|
|
|
| MMC_CMD_SWITCH_VALUE(MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED),
|
|
|
|
|
&result, CEATA_COMMAND_TIMEOUT), 3, 0);
|
|
|
|
|
if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(1);
|
|
|
|
|
if (buswidth > 1)
|
|
|
|
|
{
|
|
|
|
|
int setting;
|
|
|
|
|
if (buswidth == 4) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT;
|
|
|
|
|
else if (buswidth == 8) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT;
|
|
|
|
|
else setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT;
|
|
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
|
|
|
|
|
| MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_BUS_WIDTH)
|
|
|
|
|
| MMC_CMD_SWITCH_VALUE(setting),
|
|
|
|
|
&result, CEATA_COMMAND_TIMEOUT), 3, 2);
|
|
|
|
|
if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(3);
|
|
|
|
|
if (buswidth == 4)
|
|
|
|
|
SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_4BIT;
|
|
|
|
|
else if (buswidth == 8)
|
|
|
|
|
SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_8BIT;
|
|
|
|
|
}
|
|
|
|
|
PASS_RC(ceata_soft_reset(), 3, 4);
|
|
|
|
|
PASS_RC(ceata_read_multiple_register(0, ceata_taskfile, 0x10), 3, 5);
|
|
|
|
|
if (ceata_taskfile[0xc] != 0xce || ceata_taskfile[0xd] != 0xaa) RET_ERR(6);
|
|
|
|
|
PASS_RC(mmc_fastio_write(6, 0), 3, 7);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_check_error(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
uint32_t status, error;
|
|
|
|
|
PASS_RC(mmc_fastio_read(0xf, &status), 2, 0);
|
|
|
|
|
if (status & 1)
|
|
|
|
|
{
|
|
|
|
|
PASS_RC(mmc_fastio_read(0x9, &error), 2, 1);
|
|
|
|
|
RET_ERR((error << 2) | 2);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_wait_idle(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
long startusec = USEC_TIMER;
|
|
|
|
|
while (true)
|
|
|
|
|
{
|
|
|
|
|
uint32_t status;
|
|
|
|
|
PASS_RC(mmc_fastio_read(0xf, &status), 1, 0);
|
|
|
|
|
if (!(status & 0x88)) return 0;
|
|
|
|
|
if (TIMEOUT_EXPIRED(startusec, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(1);
|
|
|
|
|
sleep(HZ / 20);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_cancel_command(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
*((uint32_t volatile*)0x3cf00200) = 0x9000e;
|
|
|
|
|
udelay(1);
|
|
|
|
|
*((uint32_t volatile*)0x3cf00200) = 0x9000f;
|
|
|
|
|
udelay(1);
|
|
|
|
|
*((uint32_t volatile*)0x3cf00200) = 0x90003;
|
|
|
|
|
udelay(1);
|
|
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_STOP_TRANSMISSION)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
0, NULL, CEATA_COMMAND_TIMEOUT), 1, 0);
|
|
|
|
|
PASS_RC(ceata_wait_idle(), 1, 1);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ceata_rw_multiple_block(bool write, void* buf, uint32_t count, long timeout)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
mmc_discard_irq();
|
|
|
|
|
uint32_t responsetype;
|
|
|
|
|
uint32_t cmdtype;
|
|
|
|
|
uint32_t direction;
|
|
|
|
|
if (write)
|
|
|
|
|
{
|
|
|
|
|
cmdtype = SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR;
|
|
|
|
|
responsetype = SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY;
|
|
|
|
|
direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
cmdtype = SDCI_CMD_CMD_TYPE_ADTC;
|
|
|
|
|
responsetype = SDCI_CMD_RES_TYPE_R1;
|
|
|
|
|
direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ;
|
|
|
|
|
}
|
|
|
|
|
SDCI_DMASIZE = 0x200;
|
|
|
|
|
SDCI_DMAADDR = buf;
|
|
|
|
|
SDCI_DMACOUNT = count;
|
|
|
|
|
SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
2011-12-17 07:54:00 +00:00
|
|
|
commit_discard_dcache();
|
2011-02-27 22:47:55 +00:00
|
|
|
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
|
|
|
|
|
| SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
|
|
|
|
|
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
|
|
direction | MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),
|
2014-07-18 21:15:21 +00:00
|
|
|
NULL, CEATA_COMMAND_TIMEOUT), 3, 0);
|
2011-02-27 22:47:55 +00:00
|
|
|
if (write) SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
|
2011-03-02 08:49:38 +00:00
|
|
|
if (semaphore_wait(&mmc_wakeup, timeout) == OBJ_WAIT_TIMEDOUT)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(ceata_cancel_command(), 3, 1);
|
2011-02-27 22:47:55 +00:00
|
|
|
RET_ERR(2);
|
|
|
|
|
}
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(mmc_dsta_check_data_success(), 3, 3);
|
2011-03-02 08:49:38 +00:00
|
|
|
if (semaphore_wait(&mmc_comp_wakeup, timeout) == OBJ_WAIT_TIMEDOUT)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(ceata_cancel_command(), 3, 4);
|
|
|
|
|
RET_ERR(5);
|
2011-02-27 22:47:55 +00:00
|
|
|
}
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(ceata_check_error(), 3, 6);
|
2011-02-27 22:47:55 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ata_identify(uint16_t* buf)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
if (ceata)
|
|
|
|
|
{
|
|
|
|
|
memset(ceata_taskfile, 0, 16);
|
|
|
|
|
ceata_taskfile[0xf] = 0xec;
|
|
|
|
|
PASS_RC(ceata_wait_idle(), 2, 0);
|
|
|
|
|
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
|
|
|
|
PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT * HZ / 1000000), 2, 2);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_CSD, 0xec);
|
|
|
|
|
PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
|
2011-12-28 16:06:13 +00:00
|
|
|
for (i = 0; i < 0x100; i++) buf[i] = ata_read_cbr(&ATA_PIO_DTR);
|
2011-02-27 22:47:55 +00:00
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static void ata_set_active(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
ata_last_activity_value = current_tick;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ata_disk_is_active(void)
|
|
|
|
|
{
|
|
|
|
|
return ata_powered;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ata_set_feature(uint32_t feature, uint32_t param)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
2014-07-18 21:15:21 +00:00
|
|
|
if (ceata)
|
|
|
|
|
{
|
|
|
|
|
memset(ceata_taskfile, 0, 16);
|
|
|
|
|
ceata_taskfile[0x1] = feature;
|
|
|
|
|
ceata_taskfile[0x2] = param;
|
|
|
|
|
ceata_taskfile[0xf] = 0xef;
|
|
|
|
|
PASS_RC(ceata_wait_idle(), 2, 0);
|
|
|
|
|
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
|
|
|
|
PASS_RC(ceata_wait_idle(), 2, 2);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
PASS_RC(ata_wait_for_rdy(2000000), 2, 0);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_FED, feature);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_SCR, param);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_CSD, 0xef);
|
|
|
|
|
PASS_RC(ata_wait_for_rdy(2000000), 2, 1);
|
|
|
|
|
}
|
2011-02-27 22:47:55 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
iPod Classic: optimize UDMA timming for ATA drives
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
2016-05-15 00:32:40 +00:00
|
|
|
/*
|
|
|
|
|
* ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
|
|
|
|
|
* included in s5l8700 datasheet is wrong or not valid for s5l8702.
|
|
|
|
|
*
|
|
|
|
|
* On Classic (boosted):
|
|
|
|
|
* HClk = 108 MHz. -> T = ~9.26 ns.
|
|
|
|
|
*
|
|
|
|
|
* Configured values (in nanoseconds):
|
|
|
|
|
*
|
|
|
|
|
* UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
|
|
|
|
|
* 0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
|
|
|
|
|
* 1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
|
|
|
|
|
* 2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
|
|
|
|
|
* 3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
|
|
|
|
|
* 4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
|
|
|
|
|
*
|
|
|
|
|
* Tcyc = tDVS+tDVH
|
|
|
|
|
* WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
|
|
|
|
|
*/
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ata_power_up(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
ata_set_active();
|
|
|
|
|
ide_power_enable(true);
|
|
|
|
|
long spinup_start = current_tick;
|
|
|
|
|
if (ceata)
|
|
|
|
|
{
|
2014-07-18 21:15:21 +00:00
|
|
|
ata_lba48 = true;
|
|
|
|
|
ata_dma = true;
|
|
|
|
|
PCON(8) = 0x33333333;
|
|
|
|
|
PCON(9) = 0x00000033;
|
|
|
|
|
PCON(11) |= 0xf;
|
|
|
|
|
*((uint32_t volatile*)0x38a00000) = 0;
|
|
|
|
|
*((uint32_t volatile*)0x38700000) = 0;
|
2011-02-27 22:47:55 +00:00
|
|
|
PWRCON(0) &= ~(1 << 9);
|
|
|
|
|
SDCI_RESET = 0xa5;
|
|
|
|
|
sleep(HZ / 100);
|
|
|
|
|
*((uint32_t volatile*)0x3cf00380) = 0;
|
|
|
|
|
*((uint32_t volatile*)0x3cf0010c) = 0xff;
|
|
|
|
|
SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
|
|
|
|
|
| SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
|
|
|
|
|
SDCI_CDIV = SDCI_CDIV_CLKDIV(260);
|
|
|
|
|
*((uint32_t volatile*)0x3cf00200) = 0xb000f;
|
|
|
|
|
SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(mmc_init(), 3, 0);
|
2011-02-27 22:47:55 +00:00
|
|
|
SDCI_CDIV = SDCI_CDIV_CLKDIV(4);
|
|
|
|
|
sleep(HZ / 100);
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(ceata_init(8), 3, 1);
|
|
|
|
|
PASS_RC(ata_identify(ata_identify_data), 3, 2);
|
2011-02-27 22:47:55 +00:00
|
|
|
dma_mode = 0x44;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2014-07-18 21:15:21 +00:00
|
|
|
PCON(7) = 0x44444444;
|
|
|
|
|
PCON(8) = 0x44444444;
|
|
|
|
|
PCON(9) = 0x44444444;
|
|
|
|
|
PCON(10) = (PCON(10) & ~0xffff) | 0x4444;
|
2011-02-27 22:47:55 +00:00
|
|
|
PWRCON(0) &= ~(1 << 5);
|
|
|
|
|
ATA_CFG = BIT(0);
|
|
|
|
|
sleep(HZ / 100);
|
|
|
|
|
ATA_CFG = 0;
|
|
|
|
|
sleep(HZ / 100);
|
|
|
|
|
ATA_SWRST = BIT(0);
|
|
|
|
|
sleep(HZ / 100);
|
|
|
|
|
ATA_SWRST = 0;
|
|
|
|
|
sleep(HZ / 10);
|
|
|
|
|
ATA_CONTROL = BIT(0);
|
|
|
|
|
sleep(HZ / 5);
|
|
|
|
|
ATA_PIO_TIME = 0x191f7;
|
|
|
|
|
ATA_PIO_LHR = 0;
|
2016-02-05 13:04:45 +00:00
|
|
|
ATA_CFG = BIT(6);
|
2011-02-27 22:47:55 +00:00
|
|
|
while (!(ATA_PIO_READY & BIT(1))) yield();
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(ata_identify(ata_identify_data), 3, 3);
|
2011-02-27 22:47:55 +00:00
|
|
|
uint32_t piotime = 0x11f3;
|
|
|
|
|
uint32_t mdmatime = 0x1c175;
|
iPod Classic: optimize UDMA timming for ATA drives
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
2016-05-15 00:32:40 +00:00
|
|
|
uint32_t udmatime = 0x4071152;
|
2011-02-27 22:47:55 +00:00
|
|
|
uint32_t param = 0;
|
|
|
|
|
ata_dma_flags = 0;
|
|
|
|
|
ata_lba48 = ata_identify_data[83] & BIT(10) ? true : false;
|
|
|
|
|
if (ata_identify_data[53] & BIT(1))
|
|
|
|
|
{
|
|
|
|
|
if (ata_identify_data[64] & BIT(1)) piotime = 0x2072;
|
|
|
|
|
else if (ata_identify_data[64] & BIT(0)) piotime = 0x7083;
|
|
|
|
|
}
|
|
|
|
|
if (ata_identify_data[63] & BIT(2))
|
|
|
|
|
{
|
|
|
|
|
mdmatime = 0x5072;
|
|
|
|
|
param = 0x22;
|
|
|
|
|
}
|
|
|
|
|
else if (ata_identify_data[63] & BIT(1))
|
|
|
|
|
{
|
|
|
|
|
mdmatime = 0x7083;
|
|
|
|
|
param = 0x21;
|
|
|
|
|
}
|
|
|
|
|
if (ata_identify_data[63] & BITRANGE(0, 2))
|
|
|
|
|
{
|
|
|
|
|
ata_dma_flags = BIT(3) | BIT(10);
|
|
|
|
|
param |= 0x20;
|
|
|
|
|
}
|
|
|
|
|
if (ata_identify_data[53] & BIT(2))
|
|
|
|
|
{
|
|
|
|
|
if (ata_identify_data[88] & BIT(4))
|
|
|
|
|
{
|
iPod Classic: optimize UDMA timming for ATA drives
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
2016-05-15 00:32:40 +00:00
|
|
|
udmatime = 0x1010a52;
|
2011-02-27 22:47:55 +00:00
|
|
|
param = 0x44;
|
|
|
|
|
}
|
|
|
|
|
else if (ata_identify_data[88] & BIT(3))
|
|
|
|
|
{
|
iPod Classic: optimize UDMA timming for ATA drives
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
2016-05-15 00:32:40 +00:00
|
|
|
udmatime = 0x1020a52;
|
2011-02-27 22:47:55 +00:00
|
|
|
param = 0x43;
|
|
|
|
|
}
|
|
|
|
|
else if (ata_identify_data[88] & BIT(2))
|
|
|
|
|
{
|
iPod Classic: optimize UDMA timming for ATA drives
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
2016-05-15 00:32:40 +00:00
|
|
|
udmatime = 0x2030a52;
|
2011-02-27 22:47:55 +00:00
|
|
|
param = 0x42;
|
|
|
|
|
}
|
|
|
|
|
else if (ata_identify_data[88] & BIT(1))
|
|
|
|
|
{
|
iPod Classic: optimize UDMA timming for ATA drives
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
2016-05-15 00:32:40 +00:00
|
|
|
udmatime = 0x2050d52;
|
2011-02-27 22:47:55 +00:00
|
|
|
param = 0x41;
|
|
|
|
|
}
|
2016-02-12 00:06:31 +00:00
|
|
|
else if (ata_identify_data[88] & BIT(0))
|
|
|
|
|
{
|
|
|
|
|
param = 0x40;
|
|
|
|
|
}
|
2011-02-27 22:47:55 +00:00
|
|
|
if (ata_identify_data[88] & BITRANGE(0, 4))
|
|
|
|
|
{
|
|
|
|
|
ata_dma_flags = BIT(2) | BIT(3) | BIT(9) | BIT(10);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
ata_dma = param ? true : false;
|
|
|
|
|
dma_mode = param;
|
2014-07-18 21:15:21 +00:00
|
|
|
PASS_RC(ata_set_feature(0x03, param), 3, 4);
|
2015-07-16 21:10:38 +00:00
|
|
|
if (ata_identify_data[82] & BIT(5))
|
2016-02-14 11:58:36 +00:00
|
|
|
PASS_RC(ata_set_feature(0x02, 0), 3, 5);
|
2015-07-16 21:10:38 +00:00
|
|
|
if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0xaa, 0), 3, 6);
|
2011-02-27 22:47:55 +00:00
|
|
|
ATA_PIO_TIME = piotime;
|
|
|
|
|
ATA_MDMA_TIME = mdmatime;
|
|
|
|
|
ATA_UDMA_TIME = udmatime;
|
|
|
|
|
}
|
|
|
|
|
spinup_time = current_tick - spinup_start;
|
|
|
|
|
if (ata_lba48)
|
|
|
|
|
ata_total_sectors = ata_identify_data[100]
|
|
|
|
|
| (((uint64_t)ata_identify_data[101]) << 16)
|
|
|
|
|
| (((uint64_t)ata_identify_data[102]) << 32)
|
|
|
|
|
| (((uint64_t)ata_identify_data[103]) << 48);
|
|
|
|
|
else ata_total_sectors = ata_identify_data[60] | (((uint32_t)ata_identify_data[61]) << 16);
|
|
|
|
|
ata_total_sectors >>= 3;
|
|
|
|
|
ata_powered = true;
|
|
|
|
|
ata_set_active();
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static void ata_power_down(void)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
if (!ata_powered) return;
|
|
|
|
|
if (ceata)
|
|
|
|
|
{
|
|
|
|
|
memset(ceata_taskfile, 0, 16);
|
|
|
|
|
ceata_taskfile[0xf] = 0xe0;
|
|
|
|
|
ceata_wait_idle();
|
|
|
|
|
ceata_write_multiple_register(0, ceata_taskfile, 16);
|
2014-07-18 21:15:21 +00:00
|
|
|
ceata_wait_idle();
|
2011-02-27 22:47:55 +00:00
|
|
|
sleep(HZ);
|
|
|
|
|
PWRCON(0) |= (1 << 9);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
ata_wait_for_rdy(1000000);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_CSD, 0xe0);
|
|
|
|
|
ata_wait_for_rdy(1000000);
|
|
|
|
|
sleep(HZ / 30);
|
|
|
|
|
ATA_CONTROL = 0;
|
|
|
|
|
while (!(ATA_CONTROL & BIT(1))) yield();
|
|
|
|
|
PWRCON(0) |= (1 << 5);
|
|
|
|
|
}
|
2014-07-18 21:15:21 +00:00
|
|
|
PCON(7) = 0;
|
|
|
|
|
PCON(8) = 0;
|
|
|
|
|
PCON(9) = 0;
|
|
|
|
|
PCON(10) &= ~0xffff;
|
|
|
|
|
PCON(11) &= ~0xf;
|
2011-02-27 22:47:55 +00:00
|
|
|
ide_power_enable(false);
|
2016-05-15 01:11:17 +00:00
|
|
|
ata_powered = false;
|
2011-02-27 22:47:55 +00:00
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ata_rw_chunk_internal(uint64_t sector, uint32_t cnt, void* buffer, bool write)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
if (ceata)
|
|
|
|
|
{
|
|
|
|
|
memset(ceata_taskfile, 0, 16);
|
|
|
|
|
ceata_taskfile[0x2] = cnt >> 5;
|
|
|
|
|
ceata_taskfile[0x3] = sector >> 21;
|
|
|
|
|
ceata_taskfile[0x4] = sector >> 29;
|
|
|
|
|
ceata_taskfile[0x5] = sector >> 37;
|
|
|
|
|
ceata_taskfile[0xa] = cnt << 3;
|
|
|
|
|
ceata_taskfile[0xb] = sector << 3;
|
|
|
|
|
ceata_taskfile[0xc] = sector >> 5;
|
|
|
|
|
ceata_taskfile[0xd] = sector >> 13;
|
|
|
|
|
ceata_taskfile[0xf] = write ? 0x35 : 0x25;
|
|
|
|
|
PASS_RC(ceata_wait_idle(), 2, 0);
|
|
|
|
|
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
|
|
|
|
PASS_RC(ceata_rw_multiple_block(write, buffer, cnt << 3, CEATA_COMMAND_TIMEOUT * HZ / 1000000), 2, 2);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
PASS_RC(ata_wait_for_rdy(100000), 2, 0);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
|
|
if (ata_lba48)
|
|
|
|
|
{
|
|
|
|
|
ata_write_cbr(&ATA_PIO_SCR, cnt >> 5);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LHR, (sector >> 37) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LMR, (sector >> 29) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LLR, (sector >> 21) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DVR, BIT(6));
|
|
|
|
|
if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x35 : 0x39);
|
|
|
|
|
else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x25 : 0x29);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DVR, BIT(6) | ((sector >> 21) & 0xf));
|
|
|
|
|
if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xca : 0x30);
|
|
|
|
|
else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xc8 : 0xc4);
|
|
|
|
|
}
|
|
|
|
|
if (ata_dma)
|
|
|
|
|
{
|
|
|
|
|
PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
|
|
|
|
if (write)
|
|
|
|
|
{
|
|
|
|
|
ATA_SBUF_START = buffer;
|
|
|
|
|
ATA_SBUF_SIZE = SECTOR_SIZE * cnt;
|
|
|
|
|
ATA_CFG |= BIT(4);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
ATA_TBUF_START = buffer;
|
|
|
|
|
ATA_TBUF_SIZE = SECTOR_SIZE * cnt;
|
|
|
|
|
ATA_CFG &= ~BIT(4);
|
|
|
|
|
}
|
|
|
|
|
ATA_XFR_NUM = SECTOR_SIZE * cnt - 1;
|
|
|
|
|
ATA_CFG |= ata_dma_flags;
|
|
|
|
|
ATA_CFG &= ~(BIT(7) | BIT(8));
|
2011-03-02 08:49:38 +00:00
|
|
|
semaphore_wait(&ata_wakeup, 0);
|
2011-02-27 22:47:55 +00:00
|
|
|
ATA_IRQ = BITRANGE(0, 4);
|
|
|
|
|
ATA_IRQ_MASK = BIT(0);
|
|
|
|
|
ATA_COMMAND = BIT(0);
|
2011-03-02 08:49:38 +00:00
|
|
|
if (semaphore_wait(&ata_wakeup, 500000 * HZ / 1000000)
|
|
|
|
|
== OBJ_WAIT_TIMEDOUT)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
ATA_COMMAND = BIT(1);
|
|
|
|
|
ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
|
|
|
|
|
RET_ERR(2);
|
|
|
|
|
}
|
|
|
|
|
ATA_COMMAND = BIT(1);
|
|
|
|
|
ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
cnt *= SECTOR_SIZE / 512;
|
|
|
|
|
while (cnt--)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
|
|
|
|
if (write)
|
|
|
|
|
for (i = 0; i < 256; i++)
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)buffer)[i]);
|
|
|
|
|
else
|
|
|
|
|
for (i = 0; i < 256; i++)
|
|
|
|
|
((uint16_t*)buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
|
|
|
|
|
buffer += 512;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 3);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ata_rw_chunk(uint64_t sector, uint32_t cnt, void* buffer, bool write)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
led(true);
|
|
|
|
|
int rc = ata_rw_chunk_internal(sector, cnt, buffer, write);
|
|
|
|
|
led(false);
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
static int ata_rw_sectors(uint64_t sector, uint32_t count, void* buffer, bool write)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
2016-02-12 00:06:31 +00:00
|
|
|
if (STORAGE_OVERLAP((uint32_t)buffer))
|
Rewrite filesystem code (WIP)
This patch redoes the filesystem code from the FAT driver up to the
clipboard code in onplay.c.
Not every aspect of this is finished therefore it is still "WIP". I
don't wish to do too much at once (haha!). What is left to do is get
dircache back in the sim and find an implementation for the dircache
indicies in the tagcache and playlist code or do something else that
has the same benefit. Leaving these out for now does not make anything
unusable. All the basics are done.
Phone app code should probably get vetted (and app path handling
just plain rewritten as environment expansions); the SDL app and
Android run well.
Main things addressed:
1) Thread safety: There is none right now in the trunk code. Most of
what currently works is luck when multiple threads are involved or
multiple descriptors to the same file are open.
2) POSIX compliance: Many of the functions behave nothing like their
counterparts on a host system. This leads to inconsistent code or very
different behavior from native to hosted. One huge offender was
rename(). Going point by point would fill a book.
3) Actual running RAM usage: Many targets will use less RAM and less
stack space (some more RAM because I upped the number of cache buffers
for large memory). There's very little memory lying fallow in rarely-used
areas (see 'Key core changes' below). Also, all targets may open the same
number of directory streams whereas before those with less than 8MB RAM
were limited to 8, not 12 implying those targets will save slightly
less.
4) Performance: The test_disk plugin shows markedly improved performance,
particularly in the area of (uncached) directory scanning, due partly to
more optimal directory reading and to a better sector cache algorithm.
Uncached times tend to be better while there is a bit of a slowdown in
dircache due to it being a bit heavier of an implementation. It's not
noticeable by a human as far as I can say.
Key core changes:
1) Files and directories share core code and data structures.
2) The filesystem code knows which descriptors refer to same file.
This ensures that changes from one stream are appropriately reflected
in every open descriptor for that file (fileobj_mgr.c).
3) File and directory cache buffers are borrowed from the main sector
cache. This means that when they are not in use by a file, they are not
wasted, but used for the cache. Most of the time, only a few of them
are needed. It also means that adding more file and directory handles
is less expensive. All one must do in ensure a large enough cache to
borrow from.
4) Relative path components are supported and the namespace is unified.
It does not support full relative paths to an implied current directory;
what is does support is use of "." and "..". Adding the former would
not be very difficult. The namespace is unified in the sense that
volumes may be specified several times along with relative parts, e.g.:
"/<0>/foo/../../<1>/bar" :<=> "/<1>/bar".
5) Stack usage is down due to sharing of data, static allocation and
less duplication of strings on the stack. This requires more
serialization than I would like but since the number of threads is
limited to a low number, the tradoff in favor of the stack seems
reasonable.
6) Separates and heirarchicalizes (sic) the SIM and APP filesystem
code. SIM path and volume handling is just like the target. Some
aspects of the APP file code get more straightforward (e.g. no path
hashing is needed).
Dircache:
Deserves its own section. Dircache is new but pays homage to the old.
The old one was not compatible and so it, since it got redone, does
all the stuff it always should have done such as:
1) It may be update and used at any time during the build process.
No longer has one to wait for it to finish building to do basic file
management (create, remove, rename, etc.).
2) It does not need to be either fully scanned or completely disabled;
it can be incomplete (i.e. overfilled, missing paths), still be
of benefit and be correct.
3) Handles mounting and dismounting of individual volumes which means
a full rebuild is not needed just because you pop a new SD card in the
slot. Now, because it reuses its freed entry data, may rebuild only
that volume.
4) Much more fundamental to the file code. When it is built, it is
the keeper of the master file list whether enabled or not ("disabled"
is just a state of the cache). Its must always to ready to be started
and bind all streams opened prior to being enabled.
5) Maintains any short filenames in OEM format which means that it does
not need to be rebuilt when changing the default codepage.
Miscellaneous Compatibility:
1) Update any other code that would otherwise not work such as the
hotswap mounting code in various card drivers.
2) File management: Clipboard needed updating because of the behavioral
changes. Still needs a little more work on some finer points.
3) Remove now-obsolete functionality such as the mutex's "no preempt"
flag (which was only for the prior FAT driver).
4) struct dirinfo uses time_t rather than raw FAT directory entry
time fields. I plan to follow up on genericizing everything there
(i.e. no FAT attributes).
5) unicode.c needed some redoing so that the file code does not try
try to load codepages during a scan, which is actually a problem with
the current code. The default codepage, if any is required, is now
kept in RAM separarately (bufalloced) from codepages specified to
iso_decode() (which must not be bufalloced because the conversion
may be done by playback threads).
Brings with it some additional reusable core code:
1) Revised file functions: Reusable code that does things such as
safe path concatenation and parsing without buffer limitations or
data duplication. Variants that copy or alter the input path may be
based off these.
To do:
1) Put dircache functionality back in the sim. Treating it internally
as a different kind of file system seems the best approach at this
time.
2) Restore use of dircache indexes in the playlist and database or
something effectively the same. Since the cache doesn't have to be
complete in order to be used, not getting a hit on the cache doesn't
unambiguously say if the path exists or not.
Change-Id: Ia30f3082a136253e3a0eae0784e3091d138915c8
Reviewed-on: http://gerrit.rockbox.org/566
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested: Michael Sevakis <jethead71@rockbox.org>
2013-08-06 02:02:45 +00:00
|
|
|
{
|
|
|
|
|
while (count)
|
|
|
|
|
{
|
|
|
|
|
if (write)
|
|
|
|
|
memcpy(aligned_buffer, buffer, SECTOR_SIZE);
|
|
|
|
|
|
|
|
|
|
PASS_RC(ata_rw_sectors(sector, 1, aligned_buffer, write), 0, 0);
|
|
|
|
|
|
|
|
|
|
if (!write)
|
|
|
|
|
memcpy(buffer, aligned_buffer, SECTOR_SIZE);
|
|
|
|
|
|
|
|
|
|
buffer += SECTOR_SIZE;
|
|
|
|
|
sector++;
|
|
|
|
|
count--;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-27 22:47:55 +00:00
|
|
|
if (!ata_powered) ata_power_up();
|
2016-02-14 11:58:36 +00:00
|
|
|
if (sector + count > ata_total_sectors) RET_ERR(0);
|
2011-02-27 22:47:55 +00:00
|
|
|
ata_set_active();
|
2011-12-17 07:54:00 +00:00
|
|
|
if (ata_dma && write) commit_dcache();
|
|
|
|
|
else if (ata_dma) commit_discard_dcache();
|
2011-02-27 22:47:55 +00:00
|
|
|
if (!ceata) ATA_COMMAND = BIT(1);
|
|
|
|
|
while (count)
|
|
|
|
|
{
|
|
|
|
|
uint32_t cnt = MIN(ata_lba48 ? 8192 : 32, count);
|
|
|
|
|
int rc = -1;
|
|
|
|
|
rc = ata_rw_chunk(sector, cnt, buffer, write);
|
2014-07-18 21:15:21 +00:00
|
|
|
if (rc && ata_error_srst) ata_reset();
|
2011-02-27 22:47:55 +00:00
|
|
|
if (rc && ata_retries)
|
|
|
|
|
{
|
|
|
|
|
void* buf = buffer;
|
|
|
|
|
uint64_t sect;
|
|
|
|
|
for (sect = sector; sect < sector + cnt; sect++)
|
|
|
|
|
{
|
|
|
|
|
rc = -1;
|
|
|
|
|
int tries = ata_retries;
|
|
|
|
|
while (tries-- && rc)
|
|
|
|
|
{
|
|
|
|
|
rc = ata_rw_chunk(sect, 1, buf, write);
|
2014-07-18 21:15:21 +00:00
|
|
|
if (rc && ata_error_srst) ata_reset();
|
2011-02-27 22:47:55 +00:00
|
|
|
}
|
|
|
|
|
if (rc) break;
|
|
|
|
|
buf += SECTOR_SIZE;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
PASS_RC(rc, 1, 1);
|
|
|
|
|
buffer += SECTOR_SIZE * cnt;
|
|
|
|
|
sector += cnt;
|
|
|
|
|
count -= cnt;
|
|
|
|
|
}
|
|
|
|
|
ata_set_active();
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ata_thread(void)
|
|
|
|
|
{
|
|
|
|
|
while (true)
|
|
|
|
|
{
|
|
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
if (TIME_AFTER(current_tick, ata_last_activity_value + ata_sleep_timeout) && ata_powered)
|
|
|
|
|
{
|
|
|
|
|
call_storage_idle_notifys(false);
|
|
|
|
|
ata_power_down();
|
|
|
|
|
}
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
sleep(HZ / 2);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* API Functions */
|
|
|
|
|
int ata_soft_reset(void)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
mutex_lock(&ata_mutex);
|
2014-07-18 21:15:21 +00:00
|
|
|
if (!ata_powered) PASS_RC(ata_power_up(), 1, 0);
|
2011-02-27 22:47:55 +00:00
|
|
|
ata_set_active();
|
|
|
|
|
if (ceata) rc = ceata_soft_reset();
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DAD, BIT(1) | BIT(2));
|
|
|
|
|
udelay(10);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DAD, 0);
|
2014-07-18 21:15:21 +00:00
|
|
|
rc = ata_wait_for_rdy(3000000);
|
2011-02-27 22:47:55 +00:00
|
|
|
}
|
2014-07-18 21:15:21 +00:00
|
|
|
ata_set_active();
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
PASS_RC(rc, 1, 1);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int ata_hard_reset(void)
|
|
|
|
|
{
|
|
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
PASS_RC(ata_power_up(), 0, 0);
|
|
|
|
|
ata_set_active();
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ata_reset(void)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
if (!ata_powered) PASS_RC(ata_power_up(), 2, 0);
|
|
|
|
|
ata_set_active();
|
|
|
|
|
rc = ata_soft_reset();
|
2011-02-27 22:47:55 +00:00
|
|
|
if (IS_ERR(rc))
|
|
|
|
|
{
|
2014-07-18 21:15:21 +00:00
|
|
|
rc = ata_hard_reset();
|
|
|
|
|
if (IS_ERR(rc))
|
|
|
|
|
{
|
|
|
|
|
rc = ERR_RC((rc << 2) | 1);
|
|
|
|
|
ata_power_down();
|
|
|
|
|
sleep(HZ * 3);
|
|
|
|
|
int rc2 = ata_power_up();
|
|
|
|
|
if (IS_ERR(rc2)) rc = ERR_RC((rc << 2) | 2);
|
|
|
|
|
}
|
|
|
|
|
else rc = 1;
|
2011-02-27 22:47:55 +00:00
|
|
|
}
|
|
|
|
|
ata_set_active();
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-17 16:18:22 +00:00
|
|
|
int ata_read_sectors(IF_MD(int drive,) unsigned long start, int incount,
|
2011-02-27 22:47:55 +00:00
|
|
|
void* inbuf)
|
|
|
|
|
{
|
|
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
int rc = ata_rw_sectors(start, incount, inbuf, false);
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-17 16:18:22 +00:00
|
|
|
int ata_write_sectors(IF_MD(int drive,) unsigned long start, int count,
|
2011-02-27 22:47:55 +00:00
|
|
|
const void* outbuf)
|
|
|
|
|
{
|
|
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
int rc = ata_rw_sectors(start, count, (void*)((uint32_t)outbuf), true);
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ata_spindown(int seconds)
|
|
|
|
|
{
|
|
|
|
|
ata_sleep_timeout = seconds * HZ;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ata_sleep(void)
|
|
|
|
|
{
|
|
|
|
|
ata_last_activity_value = current_tick - ata_sleep_timeout + HZ / 5;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ata_sleepnow(void)
|
|
|
|
|
{
|
|
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
ata_power_down();
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ata_close(void)
|
|
|
|
|
{
|
|
|
|
|
ata_sleepnow();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ata_spin(void)
|
|
|
|
|
{
|
|
|
|
|
ata_set_active();
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-17 16:18:22 +00:00
|
|
|
void ata_get_info(IF_MD(int drive,) struct storage_info *info)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
(*info).sector_size = SECTOR_SIZE;
|
|
|
|
|
(*info).num_sectors = ata_total_sectors;
|
|
|
|
|
(*info).vendor = "Apple";
|
|
|
|
|
(*info).product = "iPod Classic";
|
|
|
|
|
(*info).revision = "1.0";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
long ata_last_disk_activity(void)
|
|
|
|
|
{
|
|
|
|
|
return ata_last_activity_value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int ata_init(void)
|
|
|
|
|
{
|
|
|
|
|
mutex_init(&ata_mutex);
|
2011-03-02 08:49:38 +00:00
|
|
|
semaphore_init(&ata_wakeup, 1, 0);
|
|
|
|
|
semaphore_init(&mmc_wakeup, 1, 0);
|
|
|
|
|
semaphore_init(&mmc_comp_wakeup, 1, 0);
|
2011-02-27 22:47:55 +00:00
|
|
|
ceata = PDAT(11) & BIT(1);
|
|
|
|
|
ata_powered = false;
|
|
|
|
|
ata_total_sectors = 0;
|
2016-05-15 00:28:34 +00:00
|
|
|
|
2016-02-05 13:04:45 +00:00
|
|
|
/* get ata_identify_data */
|
|
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
int rc = ata_power_up();
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
if (IS_ERR(rc)) return rc;
|
|
|
|
|
|
2011-02-27 22:47:55 +00:00
|
|
|
create_thread(ata_thread, ata_stack,
|
|
|
|
|
sizeof(ata_stack), 0, "ATA idle monitor"
|
|
|
|
|
IF_PRIO(, PRIORITY_USER_INTERFACE)
|
|
|
|
|
IF_COP(, CPU));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-12-09 18:38:47 +00:00
|
|
|
#ifdef HAVE_ATA_SMART
|
|
|
|
|
static int ata_smart(uint16_t* buf)
|
|
|
|
|
{
|
2016-02-13 17:28:46 +00:00
|
|
|
if (!ata_powered) PASS_RC(ata_power_up(), 3, 0);
|
2014-12-09 18:38:47 +00:00
|
|
|
if (ceata)
|
|
|
|
|
{
|
|
|
|
|
memset(ceata_taskfile, 0, 16);
|
|
|
|
|
ceata_taskfile[0xc] = 0x4f;
|
|
|
|
|
ceata_taskfile[0xd] = 0xc2;
|
2016-02-13 17:28:46 +00:00
|
|
|
ceata_taskfile[0xe] = BIT(6);
|
2014-12-09 18:38:47 +00:00
|
|
|
ceata_taskfile[0xf] = 0xb0;
|
2016-02-13 17:28:46 +00:00
|
|
|
PASS_RC(ceata_wait_idle(), 3, 1);
|
2014-12-09 18:38:47 +00:00
|
|
|
if (((uint8_t*)ata_identify_data)[54] != 'A') /* Model != aAmsung */
|
|
|
|
|
{
|
|
|
|
|
ceata_taskfile[0x9] = 0xd8; /* SMART enable operations */
|
2016-02-13 17:28:46 +00:00
|
|
|
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 3, 2);
|
|
|
|
|
PASS_RC(ceata_check_error(), 3, 3);
|
2014-12-09 18:38:47 +00:00
|
|
|
}
|
|
|
|
|
ceata_taskfile[0x9] = 0xd0; /* SMART read data */
|
2016-02-13 17:28:46 +00:00
|
|
|
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 3, 4);
|
|
|
|
|
PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT * HZ / 1000000), 3, 5);
|
2014-12-09 18:38:47 +00:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
int i;
|
2016-02-13 17:28:46 +00:00
|
|
|
PASS_RC(ata_wait_for_not_bsy(10000000), 3, 6);
|
2014-12-09 18:38:47 +00:00
|
|
|
ata_write_cbr(&ATA_PIO_FED, 0xd0);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LMR, 0x4f);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_LHR, 0xc2);
|
|
|
|
|
ata_write_cbr(&ATA_PIO_DVR, BIT(6));
|
|
|
|
|
ata_write_cbr(&ATA_PIO_CSD, 0xb0);
|
2016-02-13 17:28:46 +00:00
|
|
|
PASS_RC(ata_wait_for_start_of_transfer(10000000), 3, 7);
|
2014-12-09 18:38:47 +00:00
|
|
|
for (i = 0; i < 0x100; i++) buf[i] = ata_read_cbr(&ATA_PIO_DTR);
|
|
|
|
|
}
|
|
|
|
|
ata_set_active();
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-02-13 17:28:46 +00:00
|
|
|
int ata_read_smart(struct ata_smart_values* smart_data)
|
2014-12-09 18:38:47 +00:00
|
|
|
{
|
2016-02-13 17:28:46 +00:00
|
|
|
mutex_lock(&ata_mutex);
|
|
|
|
|
int rc = ata_smart((uint16_t*)smart_data);
|
|
|
|
|
mutex_unlock(&ata_mutex);
|
|
|
|
|
return rc;
|
2014-12-09 18:38:47 +00:00
|
|
|
}
|
|
|
|
|
#endif /* HAVE_ATA_SMART */
|
|
|
|
|
|
2011-04-22 21:39:17 +00:00
|
|
|
#ifdef CONFIG_STORAGE_MULTI
|
|
|
|
|
static int ata_num_drives(int first_drive)
|
2011-02-27 22:47:55 +00:00
|
|
|
{
|
|
|
|
|
/* We don't care which logical drive number(s) we have been assigned */
|
|
|
|
|
(void)first_drive;
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
2011-04-22 21:39:17 +00:00
|
|
|
#endif
|
2011-02-27 22:47:55 +00:00
|
|
|
|
|
|
|
|
unsigned short* ata_get_identify(void)
|
|
|
|
|
{
|
|
|
|
|
return ata_identify_data;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int ata_spinup_time(void)
|
|
|
|
|
{
|
|
|
|
|
return spinup_time;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int ata_get_dma_mode(void)
|
|
|
|
|
{
|
|
|
|
|
return dma_mode;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void INT_ATA(void)
|
|
|
|
|
{
|
|
|
|
|
uint32_t ata_irq = ATA_IRQ;
|
|
|
|
|
ATA_IRQ = ata_irq;
|
2011-03-02 08:49:38 +00:00
|
|
|
if (ata_irq & ATA_IRQ_MASK) semaphore_release(&ata_wakeup);
|
2011-02-27 22:47:55 +00:00
|
|
|
ATA_IRQ_MASK = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void INT_MMC(void)
|
|
|
|
|
{
|
|
|
|
|
uint32_t irq = SDCI_IRQ;
|
2011-03-02 08:49:38 +00:00
|
|
|
if (irq & SDCI_IRQ_DAT_DONE_INT) semaphore_release(&mmc_wakeup);
|
|
|
|
|
if (irq & SDCI_IRQ_IOCARD_IRQ_INT) semaphore_release(&mmc_comp_wakeup);
|
2011-02-27 22:47:55 +00:00
|
|
|
SDCI_IRQ = irq;
|
|
|
|
|
}
|
2014-07-18 21:15:21 +00:00
|
|
|
|