254 lines
12 KiB
C
254 lines
12 KiB
C
|
/***************************************************************************
|
||
|
|
* __________ __ ___.
|
||
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||
|
|
* \/ \/ \/ \/ \/
|
||
|
|
* This file was automatically generated by headergen, DO NOT EDIT it.
|
||
|
|
* headergen version: 3.0.0
|
||
|
|
* x1000 version: 1.0
|
||
|
|
* x1000 authors: Aidan MacDonald
|
||
|
|
*
|
||
|
|
* Copyright (C) 2015 by the authors
|
||
|
|
*
|
||
|
|
* This program is free software; you can redistribute it and/or
|
||
|
|
* modify it under the terms of the GNU General Public License
|
||
|
|
* as published by the Free Software Foundation; either version 2
|
||
|
|
* of the License, or (at your option) any later version.
|
||
|
|
*
|
||
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||
|
|
* KIND, either express or implied.
|
||
|
|
*
|
||
|
|
****************************************************************************/
|
||
|
|
#ifndef __HEADERGEN_DMA_CHN_H__
|
||
|
|
#define __HEADERGEN_DMA_CHN_H__
|
||
|
|
|
||
|
|
#include "macro.h"
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_SA(_n1) jz_reg(DMA_CHN_SA(_n1))
|
||
|
|
#define JA_DMA_CHN_SA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x0)
|
||
|
|
#define JT_DMA_CHN_SA(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_SA(_n1) DMA_CHN_SA
|
||
|
|
#define JI_DMA_CHN_SA(_n1) (_n1)
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_TA(_n1) jz_reg(DMA_CHN_TA(_n1))
|
||
|
|
#define JA_DMA_CHN_TA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x4)
|
||
|
|
#define JT_DMA_CHN_TA(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_TA(_n1) DMA_CHN_TA
|
||
|
|
#define JI_DMA_CHN_TA(_n1) (_n1)
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_TC(_n1) jz_reg(DMA_CHN_TC(_n1))
|
||
|
|
#define JA_DMA_CHN_TC(_n1) (0xb3420000 + (_n1) * 0x20 + 0x8)
|
||
|
|
#define JT_DMA_CHN_TC(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_TC(_n1) DMA_CHN_TC
|
||
|
|
#define JI_DMA_CHN_TC(_n1) (_n1)
|
||
|
|
#define BP_DMA_CHN_TC_DOA 24
|
||
|
|
#define BM_DMA_CHN_TC_DOA 0xff000000
|
||
|
|
#define BF_DMA_CHN_TC_DOA(v) (((v) & 0xff) << 24)
|
||
|
|
#define BFM_DMA_CHN_TC_DOA(v) BM_DMA_CHN_TC_DOA
|
||
|
|
#define BF_DMA_CHN_TC_DOA_V(e) BF_DMA_CHN_TC_DOA(BV_DMA_CHN_TC_DOA__##e)
|
||
|
|
#define BFM_DMA_CHN_TC_DOA_V(v) BM_DMA_CHN_TC_DOA
|
||
|
|
#define BP_DMA_CHN_TC_CNT 0
|
||
|
|
#define BM_DMA_CHN_TC_CNT 0xffffff
|
||
|
|
#define BF_DMA_CHN_TC_CNT(v) (((v) & 0xffffff) << 0)
|
||
|
|
#define BFM_DMA_CHN_TC_CNT(v) BM_DMA_CHN_TC_CNT
|
||
|
|
#define BF_DMA_CHN_TC_CNT_V(e) BF_DMA_CHN_TC_CNT(BV_DMA_CHN_TC_CNT__##e)
|
||
|
|
#define BFM_DMA_CHN_TC_CNT_V(v) BM_DMA_CHN_TC_CNT
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_RT(_n1) jz_reg(DMA_CHN_RT(_n1))
|
||
|
|
#define JA_DMA_CHN_RT(_n1) (0xb3420000 + (_n1) * 0x20 + 0xc)
|
||
|
|
#define JT_DMA_CHN_RT(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_RT(_n1) DMA_CHN_RT
|
||
|
|
#define JI_DMA_CHN_RT(_n1) (_n1)
|
||
|
|
#define BP_DMA_CHN_RT_TYPE 0
|
||
|
|
#define BM_DMA_CHN_RT_TYPE 0x3f
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__DMIC_RX 0x5
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2S_TX 0x6
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2S_RX 0x7
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__AUTO 0x8
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__UART2_TX 0x10
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__UART2_RX 0x11
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__UART1_TX 0x12
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__UART1_RX 0x13
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__UART0_TX 0x14
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__UART0_RX 0x15
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__SSI_TX 0x16
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__SSI_RX 0x17
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__MSC0_TX 0x1a
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__MSC0_RX 0x1b
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__MSC1_TX 0x1c
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__MSC1_RX 0x1d
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__PCM_TX 0x20
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__PCM_RX 0x21
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2C0_TX 0x24
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2C0_RX 0x25
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2C1_TX 0x26
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2C1_RX 0x27
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2C2_TX 0x28
|
||
|
|
#define BV_DMA_CHN_RT_TYPE__I2C2_RX 0x29
|
||
|
|
#define BF_DMA_CHN_RT_TYPE(v) (((v) & 0x3f) << 0)
|
||
|
|
#define BFM_DMA_CHN_RT_TYPE(v) BM_DMA_CHN_RT_TYPE
|
||
|
|
#define BF_DMA_CHN_RT_TYPE_V(e) BF_DMA_CHN_RT_TYPE(BV_DMA_CHN_RT_TYPE__##e)
|
||
|
|
#define BFM_DMA_CHN_RT_TYPE_V(v) BM_DMA_CHN_RT_TYPE
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_CS(_n1) jz_reg(DMA_CHN_CS(_n1))
|
||
|
|
#define JA_DMA_CHN_CS(_n1) (0xb3420000 + (_n1) * 0x20 + 0x10)
|
||
|
|
#define JT_DMA_CHN_CS(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_CS(_n1) DMA_CHN_CS
|
||
|
|
#define JI_DMA_CHN_CS(_n1) (_n1)
|
||
|
|
#define BP_DMA_CHN_CS_CDOA 8
|
||
|
|
#define BM_DMA_CHN_CS_CDOA 0xff00
|
||
|
|
#define BF_DMA_CHN_CS_CDOA(v) (((v) & 0xff) << 8)
|
||
|
|
#define BFM_DMA_CHN_CS_CDOA(v) BM_DMA_CHN_CS_CDOA
|
||
|
|
#define BF_DMA_CHN_CS_CDOA_V(e) BF_DMA_CHN_CS_CDOA(BV_DMA_CHN_CS_CDOA__##e)
|
||
|
|
#define BFM_DMA_CHN_CS_CDOA_V(v) BM_DMA_CHN_CS_CDOA
|
||
|
|
#define BP_DMA_CHN_CS_NDES 31
|
||
|
|
#define BM_DMA_CHN_CS_NDES 0x80000000
|
||
|
|
#define BF_DMA_CHN_CS_NDES(v) (((v) & 0x1) << 31)
|
||
|
|
#define BFM_DMA_CHN_CS_NDES(v) BM_DMA_CHN_CS_NDES
|
||
|
|
#define BF_DMA_CHN_CS_NDES_V(e) BF_DMA_CHN_CS_NDES(BV_DMA_CHN_CS_NDES__##e)
|
||
|
|
#define BFM_DMA_CHN_CS_NDES_V(v) BM_DMA_CHN_CS_NDES
|
||
|
|
#define BP_DMA_CHN_CS_DES8 30
|
||
|
|
#define BM_DMA_CHN_CS_DES8 0x40000000
|
||
|
|
#define BF_DMA_CHN_CS_DES8(v) (((v) & 0x1) << 30)
|
||
|
|
#define BFM_DMA_CHN_CS_DES8(v) BM_DMA_CHN_CS_DES8
|
||
|
|
#define BF_DMA_CHN_CS_DES8_V(e) BF_DMA_CHN_CS_DES8(BV_DMA_CHN_CS_DES8__##e)
|
||
|
|
#define BFM_DMA_CHN_CS_DES8_V(v) BM_DMA_CHN_CS_DES8
|
||
|
|
#define BP_DMA_CHN_CS_AR 4
|
||
|
|
#define BM_DMA_CHN_CS_AR 0x10
|
||
|
|
#define BF_DMA_CHN_CS_AR(v) (((v) & 0x1) << 4)
|
||
|
|
#define BFM_DMA_CHN_CS_AR(v) BM_DMA_CHN_CS_AR
|
||
|
|
#define BF_DMA_CHN_CS_AR_V(e) BF_DMA_CHN_CS_AR(BV_DMA_CHN_CS_AR__##e)
|
||
|
|
#define BFM_DMA_CHN_CS_AR_V(v) BM_DMA_CHN_CS_AR
|
||
|
|
#define BP_DMA_CHN_CS_TT 3
|
||
|
|
#define BM_DMA_CHN_CS_TT 0x8
|
||
|
|
#define BF_DMA_CHN_CS_TT(v) (((v) & 0x1) << 3)
|
||
|
|
#define BFM_DMA_CHN_CS_TT(v) BM_DMA_CHN_CS_TT
|
||
|
|
#define BF_DMA_CHN_CS_TT_V(e) BF_DMA_CHN_CS_TT(BV_DMA_CHN_CS_TT__##e)
|
||
|
|
#define BFM_DMA_CHN_CS_TT_V(v) BM_DMA_CHN_CS_TT
|
||
|
|
#define BP_DMA_CHN_CS_HLT 2
|
||
|
|
#define BM_DMA_CHN_CS_HLT 0x4
|
||
|
|
#define BF_DMA_CHN_CS_HLT(v) (((v) & 0x1) << 2)
|
||
|
|
#define BFM_DMA_CHN_CS_HLT(v) BM_DMA_CHN_CS_HLT
|
||
|
|
#define BF_DMA_CHN_CS_HLT_V(e) BF_DMA_CHN_CS_HLT(BV_DMA_CHN_CS_HLT__##e)
|
||
|
|
#define BFM_DMA_CHN_CS_HLT_V(v) BM_DMA_CHN_CS_HLT
|
||
|
|
#define BP_DMA_CHN_CS_CTE 0
|
||
|
|
#define BM_DMA_CHN_CS_CTE 0x1
|
||
|
|
#define BF_DMA_CHN_CS_CTE(v) (((v) & 0x1) << 0)
|
||
|
|
#define BFM_DMA_CHN_CS_CTE(v) BM_DMA_CHN_CS_CTE
|
||
|
|
#define BF_DMA_CHN_CS_CTE_V(e) BF_DMA_CHN_CS_CTE(BV_DMA_CHN_CS_CTE__##e)
|
||
|
|
#define BFM_DMA_CHN_CS_CTE_V(v) BM_DMA_CHN_CS_CTE
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_CM(_n1) jz_reg(DMA_CHN_CM(_n1))
|
||
|
|
#define JA_DMA_CHN_CM(_n1) (0xb3420000 + (_n1) * 0x20 + 0x14)
|
||
|
|
#define JT_DMA_CHN_CM(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_CM(_n1) DMA_CHN_CM
|
||
|
|
#define JI_DMA_CHN_CM(_n1) (_n1)
|
||
|
|
#define BP_DMA_CHN_CM_RDIL 16
|
||
|
|
#define BM_DMA_CHN_CM_RDIL 0xf0000
|
||
|
|
#define BF_DMA_CHN_CM_RDIL(v) (((v) & 0xf) << 16)
|
||
|
|
#define BFM_DMA_CHN_CM_RDIL(v) BM_DMA_CHN_CM_RDIL
|
||
|
|
#define BF_DMA_CHN_CM_RDIL_V(e) BF_DMA_CHN_CM_RDIL(BV_DMA_CHN_CM_RDIL__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_RDIL_V(v) BM_DMA_CHN_CM_RDIL
|
||
|
|
#define BP_DMA_CHN_CM_SP 14
|
||
|
|
#define BM_DMA_CHN_CM_SP 0xc000
|
||
|
|
#define BV_DMA_CHN_CM_SP__32BIT 0x0
|
||
|
|
#define BV_DMA_CHN_CM_SP__8BIT 0x1
|
||
|
|
#define BV_DMA_CHN_CM_SP__16BIT 0x2
|
||
|
|
#define BF_DMA_CHN_CM_SP(v) (((v) & 0x3) << 14)
|
||
|
|
#define BFM_DMA_CHN_CM_SP(v) BM_DMA_CHN_CM_SP
|
||
|
|
#define BF_DMA_CHN_CM_SP_V(e) BF_DMA_CHN_CM_SP(BV_DMA_CHN_CM_SP__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_SP_V(v) BM_DMA_CHN_CM_SP
|
||
|
|
#define BP_DMA_CHN_CM_DP 12
|
||
|
|
#define BM_DMA_CHN_CM_DP 0x3000
|
||
|
|
#define BV_DMA_CHN_CM_DP__32BIT 0x0
|
||
|
|
#define BV_DMA_CHN_CM_DP__8BIT 0x1
|
||
|
|
#define BV_DMA_CHN_CM_DP__16BIT 0x2
|
||
|
|
#define BF_DMA_CHN_CM_DP(v) (((v) & 0x3) << 12)
|
||
|
|
#define BFM_DMA_CHN_CM_DP(v) BM_DMA_CHN_CM_DP
|
||
|
|
#define BF_DMA_CHN_CM_DP_V(e) BF_DMA_CHN_CM_DP(BV_DMA_CHN_CM_DP__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_DP_V(v) BM_DMA_CHN_CM_DP
|
||
|
|
#define BP_DMA_CHN_CM_TSZ 8
|
||
|
|
#define BM_DMA_CHN_CM_TSZ 0x700
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__32BIT 0x0
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__8BIT 0x1
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__16BIT 0x2
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__16BYTE 0x3
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__32BYTE 0x4
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__64BYTE 0x5
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__128BYTE 0x6
|
||
|
|
#define BV_DMA_CHN_CM_TSZ__AUTO 0x7
|
||
|
|
#define BF_DMA_CHN_CM_TSZ(v) (((v) & 0x7) << 8)
|
||
|
|
#define BFM_DMA_CHN_CM_TSZ(v) BM_DMA_CHN_CM_TSZ
|
||
|
|
#define BF_DMA_CHN_CM_TSZ_V(e) BF_DMA_CHN_CM_TSZ(BV_DMA_CHN_CM_TSZ__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_TSZ_V(v) BM_DMA_CHN_CM_TSZ
|
||
|
|
#define BP_DMA_CHN_CM_SAI 23
|
||
|
|
#define BM_DMA_CHN_CM_SAI 0x800000
|
||
|
|
#define BF_DMA_CHN_CM_SAI(v) (((v) & 0x1) << 23)
|
||
|
|
#define BFM_DMA_CHN_CM_SAI(v) BM_DMA_CHN_CM_SAI
|
||
|
|
#define BF_DMA_CHN_CM_SAI_V(e) BF_DMA_CHN_CM_SAI(BV_DMA_CHN_CM_SAI__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_SAI_V(v) BM_DMA_CHN_CM_SAI
|
||
|
|
#define BP_DMA_CHN_CM_DAI 22
|
||
|
|
#define BM_DMA_CHN_CM_DAI 0x400000
|
||
|
|
#define BF_DMA_CHN_CM_DAI(v) (((v) & 0x1) << 22)
|
||
|
|
#define BFM_DMA_CHN_CM_DAI(v) BM_DMA_CHN_CM_DAI
|
||
|
|
#define BF_DMA_CHN_CM_DAI_V(e) BF_DMA_CHN_CM_DAI(BV_DMA_CHN_CM_DAI__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_DAI_V(v) BM_DMA_CHN_CM_DAI
|
||
|
|
#define BP_DMA_CHN_CM_STDE 2
|
||
|
|
#define BM_DMA_CHN_CM_STDE 0x4
|
||
|
|
#define BF_DMA_CHN_CM_STDE(v) (((v) & 0x1) << 2)
|
||
|
|
#define BFM_DMA_CHN_CM_STDE(v) BM_DMA_CHN_CM_STDE
|
||
|
|
#define BF_DMA_CHN_CM_STDE_V(e) BF_DMA_CHN_CM_STDE(BV_DMA_CHN_CM_STDE__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_STDE_V(v) BM_DMA_CHN_CM_STDE
|
||
|
|
#define BP_DMA_CHN_CM_TIE 1
|
||
|
|
#define BM_DMA_CHN_CM_TIE 0x2
|
||
|
|
#define BF_DMA_CHN_CM_TIE(v) (((v) & 0x1) << 1)
|
||
|
|
#define BFM_DMA_CHN_CM_TIE(v) BM_DMA_CHN_CM_TIE
|
||
|
|
#define BF_DMA_CHN_CM_TIE_V(e) BF_DMA_CHN_CM_TIE(BV_DMA_CHN_CM_TIE__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_TIE_V(v) BM_DMA_CHN_CM_TIE
|
||
|
|
#define BP_DMA_CHN_CM_LINK 0
|
||
|
|
#define BM_DMA_CHN_CM_LINK 0x1
|
||
|
|
#define BF_DMA_CHN_CM_LINK(v) (((v) & 0x1) << 0)
|
||
|
|
#define BFM_DMA_CHN_CM_LINK(v) BM_DMA_CHN_CM_LINK
|
||
|
|
#define BF_DMA_CHN_CM_LINK_V(e) BF_DMA_CHN_CM_LINK(BV_DMA_CHN_CM_LINK__##e)
|
||
|
|
#define BFM_DMA_CHN_CM_LINK_V(v) BM_DMA_CHN_CM_LINK
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_DA(_n1) jz_reg(DMA_CHN_DA(_n1))
|
||
|
|
#define JA_DMA_CHN_DA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x18)
|
||
|
|
#define JT_DMA_CHN_DA(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_DA(_n1) DMA_CHN_DA
|
||
|
|
#define JI_DMA_CHN_DA(_n1) (_n1)
|
||
|
|
#define BP_DMA_CHN_DA_DBA 12
|
||
|
|
#define BM_DMA_CHN_DA_DBA 0xfffff000
|
||
|
|
#define BF_DMA_CHN_DA_DBA(v) (((v) & 0xfffff) << 12)
|
||
|
|
#define BFM_DMA_CHN_DA_DBA(v) BM_DMA_CHN_DA_DBA
|
||
|
|
#define BF_DMA_CHN_DA_DBA_V(e) BF_DMA_CHN_DA_DBA(BV_DMA_CHN_DA_DBA__##e)
|
||
|
|
#define BFM_DMA_CHN_DA_DBA_V(v) BM_DMA_CHN_DA_DBA
|
||
|
|
#define BP_DMA_CHN_DA_DOA 4
|
||
|
|
#define BM_DMA_CHN_DA_DOA 0xff0
|
||
|
|
#define BF_DMA_CHN_DA_DOA(v) (((v) & 0xff) << 4)
|
||
|
|
#define BFM_DMA_CHN_DA_DOA(v) BM_DMA_CHN_DA_DOA
|
||
|
|
#define BF_DMA_CHN_DA_DOA_V(e) BF_DMA_CHN_DA_DOA(BV_DMA_CHN_DA_DOA__##e)
|
||
|
|
#define BFM_DMA_CHN_DA_DOA_V(v) BM_DMA_CHN_DA_DOA
|
||
|
|
|
||
|
|
#define REG_DMA_CHN_SD(_n1) jz_reg(DMA_CHN_SD(_n1))
|
||
|
|
#define JA_DMA_CHN_SD(_n1) (0xb3420000 + (_n1) * 0x20 + 0x1c)
|
||
|
|
#define JT_DMA_CHN_SD(_n1) JIO_32_RW
|
||
|
|
#define JN_DMA_CHN_SD(_n1) DMA_CHN_SD
|
||
|
|
#define JI_DMA_CHN_SD(_n1) (_n1)
|
||
|
|
#define BP_DMA_CHN_SD_TSD 16
|
||
|
|
#define BM_DMA_CHN_SD_TSD 0xffff0000
|
||
|
|
#define BF_DMA_CHN_SD_TSD(v) (((v) & 0xffff) << 16)
|
||
|
|
#define BFM_DMA_CHN_SD_TSD(v) BM_DMA_CHN_SD_TSD
|
||
|
|
#define BF_DMA_CHN_SD_TSD_V(e) BF_DMA_CHN_SD_TSD(BV_DMA_CHN_SD_TSD__##e)
|
||
|
|
#define BFM_DMA_CHN_SD_TSD_V(v) BM_DMA_CHN_SD_TSD
|
||
|
|
#define BP_DMA_CHN_SD_SSD 0
|
||
|
|
#define BM_DMA_CHN_SD_SSD 0xffff
|
||
|
|
#define BF_DMA_CHN_SD_SSD(v) (((v) & 0xffff) << 0)
|
||
|
|
#define BFM_DMA_CHN_SD_SSD(v) BM_DMA_CHN_SD_SSD
|
||
|
|
#define BF_DMA_CHN_SD_SSD_V(e) BF_DMA_CHN_SD_SSD(BV_DMA_CHN_SD_SSD__##e)
|
||
|
|
#define BFM_DMA_CHN_SD_SSD_V(v) BM_DMA_CHN_SD_SSD
|
||
|
|
|
||
|
|
#endif /* __HEADERGEN_DMA_CHN_H__*/
|