342 lines
16 KiB
C
342 lines
16 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef USB_S3C6400X_H
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#define USB_S3C6400X_H
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#define REG32_PTR_T volatile uint32_t *
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/*** OTG PHY CONTROL REGISTERS ***/
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#define OPHYPWR *(REG32_PTR_T)(PHYBASE + 0x000)
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#define OPHYCLK *(REG32_PTR_T)(PHYBASE + 0x004)
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#define ORSTCON *(REG32_PTR_T)(PHYBASE + 0x008)
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/*** OTG LINK CORE REGISTERS ***/
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/* Core Global Registers */
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#define GOTGCTL *(REG32_PTR_T)(OTGBASE + 0x000)
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#define GOTGINT *(REG32_PTR_T)(OTGBASE + 0x004)
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#define GAHBCFG *(REG32_PTR_T)(OTGBASE + 0x008)
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#define GUSBCFG *(REG32_PTR_T)(OTGBASE + 0x00C)
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#define GRSTCTL *(REG32_PTR_T)(OTGBASE + 0x010)
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#define GINTSTS *(REG32_PTR_T)(OTGBASE + 0x014)
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#define GINTMSK *(REG32_PTR_T)(OTGBASE + 0x018)
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#define GRXSTSR *(REG32_PTR_T)(OTGBASE + 0x01C)
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#define GRXSTSP *(REG32_PTR_T)(OTGBASE + 0x020)
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#define GRXFSIZ *(REG32_PTR_T)(OTGBASE + 0x024)
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#define GNPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x028)
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#define GNPTXSTS *(REG32_PTR_T)(OTGBASE + 0x02C)
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#define HPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x100)
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#define DPTXFSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x100 + 4 * x)
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#define DPTXFSIZ1 *(REG32_PTR_T)(OTGBASE + 0x104)
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#define DPTXFSIZ2 *(REG32_PTR_T)(OTGBASE + 0x108)
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#define DPTXFSIZ3 *(REG32_PTR_T)(OTGBASE + 0x10C)
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#define DPTXFSIZ4 *(REG32_PTR_T)(OTGBASE + 0x110)
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#define DPTXFSIZ5 *(REG32_PTR_T)(OTGBASE + 0x114)
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#define DPTXFSIZ6 *(REG32_PTR_T)(OTGBASE + 0x118)
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#define DPTXFSIZ7 *(REG32_PTR_T)(OTGBASE + 0x11C)
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#define DPTXFSIZ8 *(REG32_PTR_T)(OTGBASE + 0x120)
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#define DPTXFSIZ9 *(REG32_PTR_T)(OTGBASE + 0x124)
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#define DPTXFSIZ10 *(REG32_PTR_T)(OTGBASE + 0x128)
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#define DPTXFSIZ11 *(REG32_PTR_T)(OTGBASE + 0x12C)
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#define DPTXFSIZ12 *(REG32_PTR_T)(OTGBASE + 0x130)
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#define DPTXFSIZ13 *(REG32_PTR_T)(OTGBASE + 0x134)
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#define DPTXFSIZ14 *(REG32_PTR_T)(OTGBASE + 0x138)
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#define DPTXFSIZ15 *(REG32_PTR_T)(OTGBASE + 0x13C)
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/*** HOST MODE REGISTERS ***/
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/* Host Global Registers */
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#define HCFG *(REG32_PTR_T)(OTGBASE + 0x400)
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#define HFIR *(REG32_PTR_T)(OTGBASE + 0x404)
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#define HFNUM *(REG32_PTR_T)(OTGBASE + 0x408)
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#define HPTXSTS *(REG32_PTR_T)(OTGBASE + 0x410)
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#define HAINT *(REG32_PTR_T)(OTGBASE + 0x414)
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#define HAINTMSK *(REG32_PTR_T)(OTGBASE + 0x418)
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/* Host Port Control and Status Registers */
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#define HPRT *(REG32_PTR_T)(OTGBASE + 0x440)
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/* Host Channel-Specific Registers */
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#define HCCHAR(x) *(REG32_PTR_T)(OTGBASE + 0x500 + 0x20 * x)
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#define HCSPLT(x) *(REG32_PTR_T)(OTGBASE + 0x504 + 0x20 * x)
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#define HCINT(x) *(REG32_PTR_T)(OTGBASE + 0x508 + 0x20 * x)
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#define HCINTMSK(x) *(REG32_PTR_T)(OTGBASE + 0x50C + 0x20 * x)
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#define HCTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x510 + 0x20 * x)
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#define HCDMA(x) *(REG32_PTR_T)(OTGBASE + 0x514 + 0x20 * x)
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#define HCCHAR0 *(REG32_PTR_T)(OTGBASE + 0x500)
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#define HCSPLT0 *(REG32_PTR_T)(OTGBASE + 0x504)
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#define HCINT0 *(REG32_PTR_T)(OTGBASE + 0x508)
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#define HCINTMSK0 *(REG32_PTR_T)(OTGBASE + 0x50C)
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#define HCTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x510)
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#define HCDMA0 *(REG32_PTR_T)(OTGBASE + 0x514)
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#define HCCHAR1 *(REG32_PTR_T)(OTGBASE + 0x520)
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#define HCSPLT1 *(REG32_PTR_T)(OTGBASE + 0x524)
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#define HCINT1 *(REG32_PTR_T)(OTGBASE + 0x528)
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#define HCINTMSK1 *(REG32_PTR_T)(OTGBASE + 0x52C)
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#define HCTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x530)
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#define HCDMA1 *(REG32_PTR_T)(OTGBASE + 0x534)
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#define HCCHAR2 *(REG32_PTR_T)(OTGBASE + 0x540)
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#define HCSPLT2 *(REG32_PTR_T)(OTGBASE + 0x544)
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#define HCINT2 *(REG32_PTR_T)(OTGBASE + 0x548)
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#define HCINTMSK2 *(REG32_PTR_T)(OTGBASE + 0x54C)
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#define HCTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x550)
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#define HCDMA2 *(REG32_PTR_T)(OTGBASE + 0x554)
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#define HCCHAR3 *(REG32_PTR_T)(OTGBASE + 0x560)
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#define HCSPLT3 *(REG32_PTR_T)(OTGBASE + 0x564)
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#define HCINT3 *(REG32_PTR_T)(OTGBASE + 0x568)
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#define HCINTMSK3 *(REG32_PTR_T)(OTGBASE + 0x56C)
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#define HCTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x570)
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#define HCDMA3 *(REG32_PTR_T)(OTGBASE + 0x574)
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#define HCCHAR4 *(REG32_PTR_T)(OTGBASE + 0x580)
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#define HCSPLT4 *(REG32_PTR_T)(OTGBASE + 0x584)
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#define HCINT4 *(REG32_PTR_T)(OTGBASE + 0x588)
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#define HCINTMSK4 *(REG32_PTR_T)(OTGBASE + 0x58C)
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#define HCTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x590)
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#define HCDMA4 *(REG32_PTR_T)(OTGBASE + 0x594)
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#define HCCHAR5 *(REG32_PTR_T)(OTGBASE + 0x5A0)
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#define HCSPLT5 *(REG32_PTR_T)(OTGBASE + 0x5A4)
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#define HCINT5 *(REG32_PTR_T)(OTGBASE + 0x5A8)
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#define HCINTMSK5 *(REG32_PTR_T)(OTGBASE + 0x5AC)
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#define HCTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x5B0)
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#define HCDMA5 *(REG32_PTR_T)(OTGBASE + 0x5B4)
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#define HCCHAR6 *(REG32_PTR_T)(OTGBASE + 0x5C0)
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#define HCSPLT6 *(REG32_PTR_T)(OTGBASE + 0x5C4)
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#define HCINT6 *(REG32_PTR_T)(OTGBASE + 0x5C8)
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#define HCINTMSK6 *(REG32_PTR_T)(OTGBASE + 0x5CC)
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#define HCTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x5D0)
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#define HCDMA6 *(REG32_PTR_T)(OTGBASE + 0x5D4)
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#define HCCHAR7 *(REG32_PTR_T)(OTGBASE + 0x5E0)
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#define HCSPLT7 *(REG32_PTR_T)(OTGBASE + 0x5E4)
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#define HCINT7 *(REG32_PTR_T)(OTGBASE + 0x5E8)
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#define HCINTMSK7 *(REG32_PTR_T)(OTGBASE + 0x5EC)
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#define HCTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x5F0)
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#define HCDMA7 *(REG32_PTR_T)(OTGBASE + 0x5F4)
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#define HCCHAR8 *(REG32_PTR_T)(OTGBASE + 0x600)
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#define HCSPLT8 *(REG32_PTR_T)(OTGBASE + 0x604)
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#define HCINT8 *(REG32_PTR_T)(OTGBASE + 0x608)
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#define HCINTMSK8 *(REG32_PTR_T)(OTGBASE + 0x60C)
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#define HCTSIZ8 *(REG32_PTR_T)(OTGBASE + 0x610)
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#define HCDMA8 *(REG32_PTR_T)(OTGBASE + 0x614)
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#define HCCHAR9 *(REG32_PTR_T)(OTGBASE + 0x620)
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#define HCSPLT9 *(REG32_PTR_T)(OTGBASE + 0x624)
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#define HCINT9 *(REG32_PTR_T)(OTGBASE + 0x628)
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#define HCINTMSK9 *(REG32_PTR_T)(OTGBASE + 0x62C)
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#define HCTSIZ9 *(REG32_PTR_T)(OTGBASE + 0x630)
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#define HCDMA9 *(REG32_PTR_T)(OTGBASE + 0x634)
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#define HCCHAR10 *(REG32_PTR_T)(OTGBASE + 0x640)
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#define HCSPLT10 *(REG32_PTR_T)(OTGBASE + 0x644)
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#define HCINT10 *(REG32_PTR_T)(OTGBASE + 0x648)
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#define HCINTMSK10 *(REG32_PTR_T)(OTGBASE + 0x64C)
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#define HCTSIZ10 *(REG32_PTR_T)(OTGBASE + 0x650)
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#define HCDMA10 *(REG32_PTR_T)(OTGBASE + 0x654)
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#define HCCHAR11 *(REG32_PTR_T)(OTGBASE + 0x660)
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#define HCSPLT11 *(REG32_PTR_T)(OTGBASE + 0x664)
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#define HCINT11 *(REG32_PTR_T)(OTGBASE + 0x668)
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#define HCINTMSK11 *(REG32_PTR_T)(OTGBASE + 0x66C)
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#define HCTSIZ11 *(REG32_PTR_T)(OTGBASE + 0x670)
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#define HCDMA11 *(REG32_PTR_T)(OTGBASE + 0x674)
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#define HCCHAR12 *(REG32_PTR_T)(OTGBASE + 0x680)
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#define HCSPLT12 *(REG32_PTR_T)(OTGBASE + 0x684)
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#define HCINT12 *(REG32_PTR_T)(OTGBASE + 0x688)
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#define HCINTMSK12 *(REG32_PTR_T)(OTGBASE + 0x68C)
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#define HCTSIZ12 *(REG32_PTR_T)(OTGBASE + 0x690)
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#define HCDMA12 *(REG32_PTR_T)(OTGBASE + 0x694)
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#define HCCHAR13 *(REG32_PTR_T)(OTGBASE + 0x6A0)
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#define HCSPLT13 *(REG32_PTR_T)(OTGBASE + 0x6A4)
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#define HCINT13 *(REG32_PTR_T)(OTGBASE + 0x6A8)
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#define HCINTMSK13 *(REG32_PTR_T)(OTGBASE + 0x6AC)
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#define HCTSIZ13 *(REG32_PTR_T)(OTGBASE + 0x6B0)
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#define HCDMA13 *(REG32_PTR_T)(OTGBASE + 0x6B4)
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#define HCCHAR14 *(REG32_PTR_T)(OTGBASE + 0x6C0)
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#define HCSPLT14 *(REG32_PTR_T)(OTGBASE + 0x6C4)
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#define HCINT14 *(REG32_PTR_T)(OTGBASE + 0x6C8)
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#define HCINTMSK14 *(REG32_PTR_T)(OTGBASE + 0x6CC)
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#define HCTSIZ14 *(REG32_PTR_T)(OTGBASE + 0x6D0)
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#define HCDMA14 *(REG32_PTR_T)(OTGBASE + 0x6D4)
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#define HCCHAR15 *(REG32_PTR_T)(OTGBASE + 0x6E0)
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#define HCSPLT15 *(REG32_PTR_T)(OTGBASE + 0x6E4)
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#define HCINT15 *(REG32_PTR_T)(OTGBASE + 0x6E8)
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#define HCINTMSK15 *(REG32_PTR_T)(OTGBASE + 0x6EC)
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#define HCTSIZ15 *(REG32_PTR_T)(OTGBASE + 0x6F0)
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#define HCDMA15 *(REG32_PTR_T)(OTGBASE + 0x6F4)
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/*** DEVICE MODE REGISTERS ***/
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/* Device Global Registers */
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#define DCFG *(REG32_PTR_T)(OTGBASE + 0x800)
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#define DCTL *(REG32_PTR_T)(OTGBASE + 0x804)
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#define DSTS *(REG32_PTR_T)(OTGBASE + 0x808)
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#define DIEPMSK *(REG32_PTR_T)(OTGBASE + 0x810)
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#define DOEPMSK *(REG32_PTR_T)(OTGBASE + 0x814)
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#define DAINT *(REG32_PTR_T)(OTGBASE + 0x818)
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#define DAINTMSK *(REG32_PTR_T)(OTGBASE + 0x81C)
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#define DTKNQR1 *(REG32_PTR_T)(OTGBASE + 0x820)
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#define DTKNQR2 *(REG32_PTR_T)(OTGBASE + 0x824)
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#define DVBUSDIS *(REG32_PTR_T)(OTGBASE + 0x828)
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#define DVBUSPULSE *(REG32_PTR_T)(OTGBASE + 0x82C)
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#define DTKNQR3 *(REG32_PTR_T)(OTGBASE + 0x830)
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#define DTKNQR4 *(REG32_PTR_T)(OTGBASE + 0x834)
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/* Device Logical IN Endpoint-Specific Registers */
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#define DIEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0x900 + 0x20 * x)
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#define DIEPINT(x) *(REG32_PTR_T)(OTGBASE + 0x908 + 0x20 * x)
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#define DIEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x910 + 0x20 * x)
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#define DIEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0x914 + 0x20 * x)
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#define DIEPCTL0 *(REG32_PTR_T)(OTGBASE + 0x900)
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#define DIEPINT0 *(REG32_PTR_T)(OTGBASE + 0x908)
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#define DIEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x910)
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#define DIEPDMA0 *(REG32_PTR_T)(OTGBASE + 0x914)
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#define DIEPCTL1 *(REG32_PTR_T)(OTGBASE + 0x920)
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#define DIEPINT1 *(REG32_PTR_T)(OTGBASE + 0x928)
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#define DIEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x930)
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#define DIEPDMA1 *(REG32_PTR_T)(OTGBASE + 0x934)
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#define DIEPCTL2 *(REG32_PTR_T)(OTGBASE + 0x940)
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#define DIEPINT2 *(REG32_PTR_T)(OTGBASE + 0x948)
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#define DIEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x950)
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#define DIEPDMA2 *(REG32_PTR_T)(OTGBASE + 0x954)
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#define DIEPCTL3 *(REG32_PTR_T)(OTGBASE + 0x960)
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#define DIEPINT3 *(REG32_PTR_T)(OTGBASE + 0x968)
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#define DIEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x970)
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#define DIEPDMA3 *(REG32_PTR_T)(OTGBASE + 0x974)
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#define DIEPCTL4 *(REG32_PTR_T)(OTGBASE + 0x980)
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#define DIEPINT4 *(REG32_PTR_T)(OTGBASE + 0x988)
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#define DIEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x990)
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#define DIEPDMA4 *(REG32_PTR_T)(OTGBASE + 0x994)
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#define DIEPCTL5 *(REG32_PTR_T)(OTGBASE + 0x9A0)
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#define DIEPINT5 *(REG32_PTR_T)(OTGBASE + 0x9A8)
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#define DIEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x9B0)
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#define DIEPDMA5 *(REG32_PTR_T)(OTGBASE + 0x9B4)
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#define DIEPCTL6 *(REG32_PTR_T)(OTGBASE + 0x9C0)
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#define DIEPINT6 *(REG32_PTR_T)(OTGBASE + 0x9C8)
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#define DIEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x9D0)
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#define DIEPDMA6 *(REG32_PTR_T)(OTGBASE + 0x9D4)
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#define DIEPCTL7 *(REG32_PTR_T)(OTGBASE + 0x9E0)
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#define DIEPINT7 *(REG32_PTR_T)(OTGBASE + 0x9E8)
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#define DIEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x9F0)
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#define DIEPDMA7 *(REG32_PTR_T)(OTGBASE + 0x9F4)
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#define DIEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xA00)
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#define DIEPINT8 *(REG32_PTR_T)(OTGBASE + 0xA08)
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#define DIEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xA10)
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#define DIEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xA14)
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#define DIEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xA20)
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#define DIEPINT9 *(REG32_PTR_T)(OTGBASE + 0xA28)
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#define DIEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xA30)
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#define DIEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xA34)
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#define DIEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xA40)
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#define DIEPINT10 *(REG32_PTR_T)(OTGBASE + 0xA48)
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#define DIEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xA50)
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#define DIEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xA54)
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#define DIEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xA60)
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#define DIEPINT11 *(REG32_PTR_T)(OTGBASE + 0xA68)
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#define DIEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xA70)
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#define DIEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xA74)
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#define DIEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xA80)
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#define DIEPINT12 *(REG32_PTR_T)(OTGBASE + 0xA88)
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#define DIEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xA90)
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#define DIEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xA94)
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#define DIEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xAA0)
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#define DIEPINT13 *(REG32_PTR_T)(OTGBASE + 0xAA8)
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#define DIEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xAB0)
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#define DIEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xAB4)
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#define DIEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xAC0)
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#define DIEPINT14 *(REG32_PTR_T)(OTGBASE + 0xAC8)
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#define DIEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xAD0)
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#define DIEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xAD4)
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#define DIEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xAE0)
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#define DIEPINT15 *(REG32_PTR_T)(OTGBASE + 0xAE8)
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#define DIEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xAF0)
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#define DIEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xAF4)
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/* Device Logical OUT Endpoint-Specific Registers */
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#define DOEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0xB00 + 0x20 * x)
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#define DOEPINT(x) *(REG32_PTR_T)(OTGBASE + 0xB08 + 0x20 * x)
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#define DOEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0xB10 + 0x20 * x)
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#define DOEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0xB14 + 0x20 * x)
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#define DOEPCTL0 *(REG32_PTR_T)(OTGBASE + 0xB00)
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#define DOEPINT0 *(REG32_PTR_T)(OTGBASE + 0xB08)
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#define DOEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0xB10)
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#define DOEPDMA0 *(REG32_PTR_T)(OTGBASE + 0xB14)
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#define DOEPCTL1 *(REG32_PTR_T)(OTGBASE + 0xB20)
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#define DOEPINT1 *(REG32_PTR_T)(OTGBASE + 0xB28)
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#define DOEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0xB30)
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#define DOEPDMA1 *(REG32_PTR_T)(OTGBASE + 0xB34)
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#define DOEPCTL2 *(REG32_PTR_T)(OTGBASE + 0xB40)
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#define DOEPINT2 *(REG32_PTR_T)(OTGBASE + 0xB48)
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#define DOEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0xB50)
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#define DOEPDMA2 *(REG32_PTR_T)(OTGBASE + 0xB54)
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#define DOEPCTL3 *(REG32_PTR_T)(OTGBASE + 0xB60)
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#define DOEPINT3 *(REG32_PTR_T)(OTGBASE + 0xB68)
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#define DOEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0xB70)
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#define DOEPDMA3 *(REG32_PTR_T)(OTGBASE + 0xB74)
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#define DOEPCTL4 *(REG32_PTR_T)(OTGBASE + 0xB80)
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#define DOEPINT4 *(REG32_PTR_T)(OTGBASE + 0xB88)
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#define DOEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0xB90)
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#define DOEPDMA4 *(REG32_PTR_T)(OTGBASE + 0xB94)
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#define DOEPCTL5 *(REG32_PTR_T)(OTGBASE + 0xBA0)
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#define DOEPINT5 *(REG32_PTR_T)(OTGBASE + 0xBA8)
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#define DOEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0xBB0)
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#define DOEPDMA5 *(REG32_PTR_T)(OTGBASE + 0xBB4)
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#define DOEPCTL6 *(REG32_PTR_T)(OTGBASE + 0xBC0)
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#define DOEPINT6 *(REG32_PTR_T)(OTGBASE + 0xBC8)
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#define DOEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0xBD0)
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#define DOEPDMA6 *(REG32_PTR_T)(OTGBASE + 0xBD4)
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||
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#define DOEPCTL7 *(REG32_PTR_T)(OTGBASE + 0xBE0)
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||
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#define DOEPINT7 *(REG32_PTR_T)(OTGBASE + 0xBE8)
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||
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#define DOEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0xBF0)
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||
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#define DOEPDMA7 *(REG32_PTR_T)(OTGBASE + 0xBF4)
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||
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#define DOEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xC00)
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||
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#define DOEPINT8 *(REG32_PTR_T)(OTGBASE + 0xC08)
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||
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#define DOEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xC10)
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||
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#define DOEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xC14)
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||
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#define DOEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xC20)
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||
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#define DOEPINT9 *(REG32_PTR_T)(OTGBASE + 0xC28)
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||
|
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#define DOEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xC30)
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||
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#define DOEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xC34)
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||
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|
#define DOEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xC40)
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||
|
|
#define DOEPINT10 *(REG32_PTR_T)(OTGBASE + 0xC48)
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||
|
|
#define DOEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xC50)
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||
|
|
#define DOEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xC54)
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||
|
|
#define DOEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xC60)
|
||
|
|
#define DOEPINT11 *(REG32_PTR_T)(OTGBASE + 0xC68)
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||
|
|
#define DOEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xC70)
|
||
|
|
#define DOEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xC74)
|
||
|
|
#define DOEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xC80)
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||
|
|
#define DOEPINT12 *(REG32_PTR_T)(OTGBASE + 0xC88)
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||
|
|
#define DOEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xC90)
|
||
|
|
#define DOEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xC94)
|
||
|
|
#define DOEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xCA0)
|
||
|
|
#define DOEPINT13 *(REG32_PTR_T)(OTGBASE + 0xCA8)
|
||
|
|
#define DOEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xCB0)
|
||
|
|
#define DOEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xCB4)
|
||
|
|
#define DOEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xCC0)
|
||
|
|
#define DOEPINT14 *(REG32_PTR_T)(OTGBASE + 0xCC8)
|
||
|
|
#define DOEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xCD0)
|
||
|
|
#define DOEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xCD4)
|
||
|
|
#define DOEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xCE0)
|
||
|
|
#define DOEPINT15 *(REG32_PTR_T)(OTGBASE + 0xCE8)
|
||
|
|
#define DOEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xCF0)
|
||
|
|
#define DOEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xCF4)
|
||
|
|
|
||
|
|
/* Power and Clock Gating Register */
|
||
|
|
#define PCGCCTL *(REG32_PTR_T)(OTGBASE + 0xE00)
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* USB_S3C6400X_H */
|