2008-05-16 21:16:01 +00:00
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;* Copyright (c) 2007, C.P.R. Baaij
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without
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;* modification, are permitted provided that the following conditions are met:
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;* * Redistributions of source code must retain the above copyright
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;* notice, this list of conditions and the following disclaimer.
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;* * Redistributions in binary form must reproduce the above copyright
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;* notice, this list of conditions and the following disclaimer in the
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;* documentation and/or other materials provided with the distribution.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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;* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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;* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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;* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*-----------------------------------------------------------------------------*
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;* Interrupt Vectors *
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;*-----------------------------------------------------------------------------*
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.mmregs
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; External Functions
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.global _handle_int0
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2009-12-02 04:30:08 +00:00
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.global _main
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2008-05-16 21:16:01 +00:00
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.global _handle_dma0
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.global _handle_dmac
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2011-02-06 19:28:46 +00:00
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.global _c_int00
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2008-05-16 21:16:01 +00:00
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.sect ".vectors"
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; Reset Interrupt
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2009-12-02 04:30:08 +00:00
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; The rtx500.lib should be included if you want proper initialization,
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; currently the program is setup so that it is not necessary to save space.
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; reset vector should jump to _c_int00 instead of main if initialization is
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; needed.
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2011-02-06 19:28:46 +00:00
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RS_V: BD _c_int00
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2008-05-16 21:16:01 +00:00
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NOP
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NOP
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; Non-Maskable Interrupt
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NMI_V: RETE
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NOP
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NOP
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NOP
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; Software Interrupts
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SINt17_V: .space 4*16
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SINt18_V: .space 4*16
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SINt19_V: .space 4*16
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SINt20_V: .space 4*16
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SINt21_V: .space 4*16
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SINt22_V: .space 4*16
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SINt23_V: .space 4*16
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SINt24_V: .space 4*16
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SINt25_V: .space 4*16
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SINt26_V: .space 4*16
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SINt27_V: .space 4*16
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SINt28_V: .space 4*16
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SINt29_V: .space 4*16
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SINt30_V: .space 4*16
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; INT0 - ARM Interrupting DSP via HPIB
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INT0_V: BD _handle_int0
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NOP
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NOP
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; INT1 - Interrupt is generated based on the settings of DSP_SYNC_STATE and
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; DSP_SYNC_MASK register of the coprocessor subsystem or when DSPINT1 bit in
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; CP_INTC is set.
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INT1_V: RETE
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NOP
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NOP
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NOP
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; INT2 - Interrupt is generated when DSPINT2 bit in CP_INTC register of the
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; coprocessor subsystem is set.
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INT2_V: RETE
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NOP
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NOP
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NOP
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; Timer Interrupt
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TINT_V: RETE
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NOP
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NOP
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NOP
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; McBSP0 receive interrupt
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BRINT0_V: RETE
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NOP
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NOP
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NOP
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; McBSP0 transmit interrupt
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BXINT0_V: RETE
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NOP
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NOP
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NOP
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; DMA Channel-0 interrupt
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DMAC0_V: BD _handle_dma0
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NOP
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NOP
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; DMA Channel-1 interrupt
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DMAC1_V: RETE
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NOP
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NOP
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NOP
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; INT3 - Interrupt is generated when DSPINT3 bit in CP_INTC register of the
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; coprocessor subsystem is set or on write of any value to BRKPT_TRG
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INT3_V: RETE
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NOP
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NOP
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NOP
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; HPIB HINT to DSP
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HINT_V: RETE
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NOP
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NOP
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NOP
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; BRINT1/DMAC2 McBSP1 receive interrupt
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BRINT1_V: RETE
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NOP
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NOP
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NOP
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; BXINT1/DMAC3 McBSP1 transmit interrupt
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BXINT1_V: RETE
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NOP
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NOP
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NOP
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; DMA Channel-4 interrupt
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DMAC4_V: RETE
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NOP
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NOP
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NOP
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; DMA Channel-5 interrupt
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DMAC5_V: RETE
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NOP
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NOP
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NOP
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; HPIB DMAC interrupt
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HPIB_DMA_V: BD _handle_dmac
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NOP
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NOP
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; EHIF interrupt to DSP
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EHIV_V: RETE
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NOP
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NOP
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NOP
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.end
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