276 lines
7.5 KiB
C
276 lines
7.5 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Rob Purchase
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#if !defined(BOOTLOADER)
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
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default_interrupt(EXT0);
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default_interrupt(EXT1);
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default_interrupt(EXT2);
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default_interrupt(EXT3);
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default_interrupt(IRQ4);
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default_interrupt(IRQ5);
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default_interrupt(TIMER);
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default_interrupt(IRQ7);
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default_interrupt(IRQ8);
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default_interrupt(IRQ9);
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default_interrupt(IRQ10);
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default_interrupt(IRQ11);
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default_interrupt(IRQ12);
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default_interrupt(IRQ13);
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default_interrupt(DAI_RX);
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default_interrupt(DAI_TX);
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default_interrupt(IRQ16);
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default_interrupt(IRQ17);
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default_interrupt(IRQ18);
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default_interrupt(IRQ19);
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default_interrupt(IRQ20);
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default_interrupt(IRQ21);
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default_interrupt(IRQ22);
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default_interrupt(IRQ23);
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default_interrupt(IRQ24);
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default_interrupt(IRQ25);
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default_interrupt(IRQ26);
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default_interrupt(IRQ27);
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default_interrupt(IRQ28);
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default_interrupt(IRQ29);
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default_interrupt(IRQ30);
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default_interrupt(IRQ31);
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static void (* const irqvector[])(void) =
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{
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EXT0,EXT1,EXT2,EXT3,IRQ4,IRQ5,TIMER,IRQ7,
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IRQ8,IRQ9,IRQ10,IRQ11,IRQ12,IRQ13,DAI_RX,DAI_TX,
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IRQ16,IRQ17,IRQ18,IRQ19,IRQ20,IRQ21,IRQ22,IRQ23,
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IRQ24,IRQ25,IRQ26,IRQ27,IRQ28,IRQ29,IRQ30,IRQ31
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};
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static const char * const irqname[] =
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{
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"EXT0","EXT1","EXT2","EXT3","IRQ4","IRQ5","TIMER","IRQ7",
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"IRQ8","IRQ9","IRQ10","IRQ11","IRQ12","IRQ13","DAI_RX","DAI_TX",
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"IRQ16","IRQ17","IRQ18","IRQ19","IRQ20","IRQ21","IRQ22","IRQ23",
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"IRQ24","IRQ25","IRQ26","IRQ27","IRQ28","IRQ29","IRQ30","IRQ31"
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};
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static void UIRQ(void)
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{
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unsigned int offset = VNIRQ;
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panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
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}
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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irqvector[VNIRQ]();
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from FIQ */
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}
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void fiq_handler(void)
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{
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asm volatile (
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"sub lr, lr, #4 \r\n"
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"movs lr,pc \r\n"
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);
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}
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#endif /* !defined(BOOTLOADER) */
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/* TODO:
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a) this is not the place for this function
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b) it currently ignores the supplied frequency and uses default values
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c) if the PLL being set drives any PCKs, an appropriate new clock divider
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will have to be re-calculated for those PCKs (the OF maintains a list of
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PCK frequencies for this purpose).
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*/
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void set_pll_frequency(unsigned int pll_number, unsigned int frequency)
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{
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int i = 0;
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if (pll_number > 1) return;
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/* The frequency parameter is currently ignored and temporary values are
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used (PLL0=192Mhz, PLL1=216Mhz). The D2 firmware uses a lookup table
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to derive the values of PLLxCFG from a the supplied frequency.
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Presumably we will need to do something similar. */
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if (pll_number == 0)
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{
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/* drive CPU off Xin while switching */
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CLKCTRL = 0xB00FF014; /* Xin enable, Fsys driven by Xin, Fbus = Fsys,
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MCPU=Fbus, SCPU=Fbus */
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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PLL0CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 24); /* disable PLL0 divider */
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PLL0CFG = 0x80019808; /* set for 192Mhz (with power down) */
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PLL0CFG = PLL0CFG &~ (1<<31); /* power up */
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CLKCTRL = (CLKCTRL & ~0x1f) | 0x800FF010;
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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}
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else if (pll_number == 1)
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{
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PLL1CFG |= (1<<31); /* power down */
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CLKDIVC = CLKDIVC &~ (0xff << 16); /* disable PLL1 divider */
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PLL1CFG = 0x80002503; /* set for 216Mhz (with power down)*/
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PLL1CFG = PLL1CFG &~ (1<<31); /* power up */
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}
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i = 0x1000;
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while (--i) {};
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}
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/* TODO - these should live in the target-specific directories and
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once we understand what all the GPIO pins do, move the init to the
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specific driver for that hardware. For now, we just perform the
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same GPIO init as the original firmware - this makes it easier to
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investigate what the GPIO pins do.
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*/
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#ifdef COWON_D2
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static void gpio_init(void)
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{
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/* Do what the original firmware does */
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GPIOA = 0x07000C83;
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GPIOA_DIR = 0x0F010CE3;
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GPIOB = 0;
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GPIOB_DIR = 0x00080000;
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GPIOC = 0x39000000;
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GPIOC_DIR = 0xB9000000;
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GPIOD = 0;
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GPIOD_DIR = 0;
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GPIOD = 0;
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GPIOD_DIR = 0x00480000;
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PORTCFG0 = 0x00034540;
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PORTCFG1 = 0x0566A000;
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PORTCFG2 = 0x000004C0;
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PORTCFG3 = 0x0AA40455;
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}
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#endif
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/* Second function called in the original firmware's startup code - we just
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set up the clocks in the same way as the original firmware for now. */
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#ifdef COWON_D2
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static void clock_init(void)
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{
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int i;
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CSCFG3 = (CSCFG3 &~ 0x3fff) | 0x841;
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CLKCTRL = (CLKCTRL & ~0xff) | 0x14;
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PCLK_RFREQ = 0x1401002d; /* RAM refresh source = Xin (4) / 0x2d = 266kHz */
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MCFG |= 1;
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SDCFG = (SDCFG &~ 0x7000) | 0x2000;
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MCFG1 |= 1;
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SDCFG1 = (SDCFG &~ 0x7000) | 0x2000;
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PLL0CFG |= 0x80000000; /* power down */
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PLL0CFG = 0x14010000; /* power up, source = Xin (4) undivided = 12Mhz */
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i = 0x8000;
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while (--i) {};
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CLKCTRL = (CLKCTRL &~ 0x1f) | 0x800FF010; /* CPU and COP driven by PLL0 */
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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/* configure PCK_TCT to 2Mhz (clock source 4 (Xin) divided by 6) */
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PCLK_TCT = PCK_EN | (CKSEL_XIN<<24) | 5;
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}
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#endif
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#ifdef COWON_D2
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void system_init(void)
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{
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MBCFG = 0x19;
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if (TCC780_VER == 0)
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ECFG0 = 0x309;
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else
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ECFG0 = 0x30d;
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/* mask all interrupts */
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MIRQ = -1;
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gpio_init();
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clock_init();
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/* TODO: these almost certainly shouldn't be here */
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set_pll_frequency(0, 192000000); /* drives CPU */
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set_pll_frequency(1, 216000000); /* drives LCD PXCLK - divided by 2 */
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}
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#endif
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void system_reboot(void)
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{
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#warning function not implemented
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}
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int system_memory_guard(int newmode)
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{
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#warning function not implemented
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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#warning function not implemented
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(void)frequency;
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}
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#endif
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