2005-02-04 08:34:20 +00:00
|
|
|
#include "config.h"
|
|
|
|
|
|
|
|
/* These output formats should be in the config-files */
|
|
|
|
|
2005-07-18 12:40:29 +00:00
|
|
|
#ifdef CPU_COLDFIRE
|
2005-02-04 08:34:20 +00:00
|
|
|
OUTPUT_FORMAT(elf32-m68k)
|
2006-01-12 00:35:50 +00:00
|
|
|
#elif defined(CPU_ARM)
|
2005-11-12 16:01:15 +00:00
|
|
|
OUTPUT_FORMAT(elf32-littlearm)
|
2009-02-09 10:02:38 +00:00
|
|
|
#elif defined(CPU_SH)
|
2003-06-29 16:33:04 +00:00
|
|
|
OUTPUT_FORMAT(elf32-sh)
|
2009-02-09 10:02:38 +00:00
|
|
|
#elif defined(CPU_MIPS)
|
|
|
|
OUTPUT_FORMAT(elf32-littlemips)
|
2009-02-09 18:31:56 +00:00
|
|
|
#else
|
|
|
|
/* We can have an #error here we don't use this file when build sims! */
|
2009-02-09 16:18:07 +00:00
|
|
|
#error Unknown CPU architecture
|
2005-02-04 08:34:20 +00:00
|
|
|
#endif
|
2003-06-29 16:33:04 +00:00
|
|
|
|
2005-02-04 12:25:18 +00:00
|
|
|
#ifdef DEBUG
|
|
|
|
#define STUBOFFSET 0x10000
|
|
|
|
#else
|
|
|
|
#define STUBOFFSET 0
|
|
|
|
#endif
|
|
|
|
|
2008-04-06 04:34:57 +00:00
|
|
|
#if defined(CPU_PP)
|
|
|
|
#ifdef CPU_PP502x
|
|
|
|
#define NOCACHE_BASE 0x10000000
|
|
|
|
#else
|
|
|
|
#define NOCACHE_BASE 0x28000000
|
|
|
|
#endif /* CPU_* */
|
|
|
|
#define CACHEALIGN_SIZE 16
|
|
|
|
#endif /* CPU_PP */
|
|
|
|
|
|
|
|
#ifndef NOCACHE_BASE
|
|
|
|
/* Default to no offset if target doesn't define this */
|
|
|
|
#define NOCACHE_BASE 0x00000000
|
|
|
|
#endif
|
|
|
|
|
2009-04-09 04:22:14 +00:00
|
|
|
#if CONFIG_CPU==DM320 || CONFIG_CPU==IMX31L
|
|
|
|
/* Give this 1 meg to allow it to align to the MMU boundary */
|
2009-06-13 20:59:03 +00:00
|
|
|
#if CONFIG_CPU==DM320
|
2009-06-13 21:26:50 +00:00
|
|
|
#ifndef LCD_NATIVE_WIDTH
|
|
|
|
#define LCD_NATIVE_WIDTH LCD_WIDTH
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef LCD_NATIVE_HEIGHT
|
|
|
|
#define LCD_NATIVE_HEIGHT LCD_HEIGHT
|
|
|
|
#endif
|
|
|
|
|
2009-06-13 20:59:03 +00:00
|
|
|
#define LCD_FUDGE LCD_NATIVE_WIDTH%32
|
|
|
|
#define LCD_BUFFER_SIZE ((LCD_NATIVE_WIDTH+LCD_FUDGE)*LCD_NATIVE_HEIGHT*2)
|
|
|
|
#define LCD_TTB_AREA 0x100000*((LCD_BUFFER_SIZE>>19)+1)
|
|
|
|
#else
|
2009-04-09 04:22:14 +00:00
|
|
|
#define LCD_TTB_AREA 0x100000
|
2009-06-13 20:59:03 +00:00
|
|
|
#endif
|
|
|
|
|
2009-04-09 04:22:14 +00:00
|
|
|
#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_TTB_AREA
|
2009-04-01 03:21:18 +00:00
|
|
|
|
2009-04-09 04:22:14 +00:00
|
|
|
#elif CONFIG_CPU==S3C2440
|
2009-05-20 23:30:24 +00:00
|
|
|
#include "cpu.h"
|
2009-04-01 03:21:18 +00:00
|
|
|
/* must be 16Kb (0x4000) aligned */
|
|
|
|
#define TTB_SIZE (0x4000)
|
2008-04-22 04:34:25 +00:00
|
|
|
#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_BUFFER_SIZE - TTB_SIZE
|
2009-04-09 04:22:14 +00:00
|
|
|
|
2009-09-01 21:35:37 +00:00
|
|
|
#elif CONFIG_CPU==TCC7801
|
|
|
|
#include "cpu.h"
|
|
|
|
#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE - CODEC_SIZE - TTB_SIZE
|
|
|
|
|
2010-02-22 02:42:58 +00:00
|
|
|
#elif CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2
|
2009-05-20 23:30:24 +00:00
|
|
|
#include "cpu.h"
|
2009-05-20 21:09:53 +00:00
|
|
|
#define DRAMORIG DRAM_ORIG
|
2010-04-05 19:18:15 +00:00
|
|
|
#if defined(AMS_LOWMEM) || (CONFIG_CPU == AS3525v2)
|
2009-05-20 21:09:53 +00:00
|
|
|
#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - STUBOFFSET - TTB_SIZE)
|
2007-09-30 16:29:21 +00:00
|
|
|
#else
|
2009-05-20 21:09:53 +00:00
|
|
|
#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE - TTB_SIZE)
|
2007-09-30 16:29:21 +00:00
|
|
|
#endif
|
2009-04-20 20:18:47 +00:00
|
|
|
#endif
|
2007-09-30 16:29:21 +00:00
|
|
|
|
2009-04-20 20:44:39 +00:00
|
|
|
/* default to full RAM (minus codecs&plugins) unless specified otherwise */
|
|
|
|
#ifndef DRAMSIZE
|
|
|
|
#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
2005-07-08 15:08:59 +00:00
|
|
|
#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300)
|
2005-06-29 13:12:45 +00:00
|
|
|
#define ARCH_IRIVER
|
|
|
|
#endif
|
|
|
|
|
2008-03-14 08:54:54 +00:00
|
|
|
#if defined(ARCH_IRIVER) || defined(IAUDIO_M3)
|
2005-04-20 18:54:20 +00:00
|
|
|
#define DRAMORIG 0x31000000
|
2005-09-01 20:57:33 +00:00
|
|
|
#define IRAMORIG 0x1000c000
|
|
|
|
#define IRAMSIZE 0xc000
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2007-03-05 00:04:00 +00:00
|
|
|
#elif defined(IAUDIO_X5) || defined(IAUDIO_M5)
|
2006-03-21 12:25:40 +00:00
|
|
|
#define DRAMORIG 0x31000000
|
2010-03-07 20:22:49 +00:00
|
|
|
#define IRAMORIG 0x1000c000
|
|
|
|
#define IRAMSIZE 0x14000
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2008-05-14 21:41:25 +00:00
|
|
|
#elif CONFIG_CPU == PP5022 || CONFIG_CPU == PP5024
|
2008-05-14 19:30:34 +00:00
|
|
|
/* PP5022/24 have 128KB of IRAM */
|
|
|
|
#define DRAMORIG 0x00000000
|
|
|
|
#define IRAMORIG 0x4000c000
|
|
|
|
#define IRAMSIZE 0x14000
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2006-11-22 00:41:30 +00:00
|
|
|
#elif defined(CPU_PP)
|
2008-05-14 19:30:34 +00:00
|
|
|
/* all other PP's have 96KB of IRAM */
|
2006-01-16 12:57:46 +00:00
|
|
|
#define DRAMORIG 0x00000000
|
2005-11-12 16:01:15 +00:00
|
|
|
#define IRAMORIG 0x4000c000
|
2008-05-14 19:30:34 +00:00
|
|
|
#define IRAMSIZE 0x0c000
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2006-01-12 00:35:50 +00:00
|
|
|
#elif CONFIG_CPU == PNX0101
|
2006-02-12 23:16:05 +00:00
|
|
|
#define DRAMORIG 0xc00000 + STUBOFFSET
|
2006-08-12 22:43:44 +00:00
|
|
|
#define IRAMORIG 0x407000
|
|
|
|
#define IRAMSIZE 0x9000
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2009-04-09 04:22:14 +00:00
|
|
|
#elif CONFIG_CPU == IMX31L || CONFIG_CPU == S3C2440
|
2008-05-02 00:38:11 +00:00
|
|
|
#define DRAMORIG 0x0 + STUBOFFSET
|
|
|
|
#define IRAM DRAM
|
2008-05-10 22:03:45 +00:00
|
|
|
#define IRAMSIZE 0
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2007-09-30 16:29:21 +00:00
|
|
|
#elif CONFIG_CPU==DM320
|
|
|
|
#define DRAMORIG 0x00900000 + STUBOFFSET
|
2007-11-02 05:21:34 +00:00
|
|
|
#define IRAM DRAM
|
2009-04-01 03:21:18 +00:00
|
|
|
/* The bit of IRAM that is available is used in the core */
|
2009-03-11 03:46:24 +00:00
|
|
|
#define IRAMSIZE 0
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2008-09-06 17:50:59 +00:00
|
|
|
#elif defined(CPU_TCC780X) || defined(CPU_TCC77X)
|
2008-01-14 22:04:48 +00:00
|
|
|
#define DRAMORIG 0x20000000
|
2008-06-24 07:38:35 +00:00
|
|
|
/*#define IRAMORIG 0x1000c000
|
|
|
|
#define IRAMSIZE 0xc000*/
|
|
|
|
#define IRAM DRAM
|
|
|
|
#define IRAMSIZE 0
|
2009-04-20 20:18:47 +00:00
|
|
|
|
2010-02-22 02:42:58 +00:00
|
|
|
#elif CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2
|
2010-04-05 19:18:15 +00:00
|
|
|
#if defined(AMS_LOWMEM) || (CONFIG_CPU == AS3525v2)
|
2008-12-04 22:27:48 +00:00
|
|
|
#define IRAMSIZE 0 /* simulates no IRAM since codec is already entirely in IRAM */
|
2009-05-20 21:09:53 +00:00
|
|
|
#define CODEC_ORIGIN (IRAM_ORIG + IRAM_SIZE - CODEC_SIZE)
|
|
|
|
#define PLUGIN_ORIGIN (DRAM_ORIG + DRAMSIZE)
|
2008-12-04 22:27:48 +00:00
|
|
|
#else
|
2009-05-20 21:09:53 +00:00
|
|
|
#define IRAMORIG (IRAM_ORIG + 0x20000)
|
|
|
|
#define IRAMSIZE (IRAM_ORIG + IRAM_SIZE - IRAMORIG)
|
2008-12-04 22:27:48 +00:00
|
|
|
#endif
|
|
|
|
|
2009-10-04 02:04:49 +00:00
|
|
|
#elif CONFIG_CPU==S5L8700
|
|
|
|
#define DRAMORIG 0x08000000
|
2010-02-17 16:12:21 +00:00
|
|
|
#define IRAMORIG (0x00000000 + (64*1024))
|
|
|
|
#define IRAMSIZE (64*1024)
|
2009-10-04 02:04:49 +00:00
|
|
|
|
|
|
|
#elif CONFIG_CPU==S5L8701
|
|
|
|
#define DRAMORIG 0x08000000
|
|
|
|
#define IRAMORIG (0x00000000 + (96*1024))
|
|
|
|
#define IRAMSIZE (80*1024)
|
|
|
|
|
2009-02-09 10:02:38 +00:00
|
|
|
#elif CONFIG_CPU == JZ4732
|
|
|
|
#define DRAMORIG 0x80004000 + STUBOFFSET
|
2009-07-30 17:07:39 +00:00
|
|
|
#define IRAM DRAM
|
2010-01-03 16:34:56 +00:00
|
|
|
#define IRAMSIZE 0
|
2009-07-30 17:07:39 +00:00
|
|
|
/* The bit of IRAM that is available is used in the core */
|
2005-02-04 12:25:18 +00:00
|
|
|
#else
|
|
|
|
#define DRAMORIG 0x09000000 + STUBOFFSET
|
|
|
|
#endif
|
|
|
|
|
2005-06-27 21:23:03 +00:00
|
|
|
#define PLUGIN_LENGTH PLUGIN_BUFFER_SIZE
|
2007-01-13 02:24:15 +00:00
|
|
|
|
2009-04-20 20:44:39 +00:00
|
|
|
|
2008-12-04 22:27:48 +00:00
|
|
|
#ifndef CODEC_ORIGIN /* targets can specify another origin */
|
2005-06-28 21:12:11 +00:00
|
|
|
#define CODEC_ORIGIN (DRAMORIG + (DRAMSIZE))
|
2008-12-04 22:27:48 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef PLUGIN_ORIGIN /* targets can specify another origin */
|
2005-06-28 21:12:11 +00:00
|
|
|
#define PLUGIN_ORIGIN (CODEC_ORIGIN + CODEC_SIZE)
|
2008-12-04 22:27:48 +00:00
|
|
|
#endif
|
2005-06-28 21:12:11 +00:00
|
|
|
|
2005-06-27 21:23:03 +00:00
|
|
|
#ifdef CODEC
|
2005-06-22 02:47:54 +00:00
|
|
|
#define THIS_LENGTH CODEC_SIZE
|
2005-06-28 21:12:11 +00:00
|
|
|
#define THIS_ORIGIN CODEC_ORIGIN
|
2009-03-02 00:16:44 +00:00
|
|
|
#elif defined OVERLAY_OFFSET
|
|
|
|
#define THIS_LENGTH (DRAMSIZE - OVERLAY_OFFSET)
|
|
|
|
#define THIS_ORIGIN (DRAMORIG + OVERLAY_OFFSET)
|
|
|
|
#else /* plugin */
|
2005-06-22 02:47:54 +00:00
|
|
|
#define THIS_LENGTH PLUGIN_LENGTH
|
2005-06-28 21:12:11 +00:00
|
|
|
#define THIS_ORIGIN PLUGIN_ORIGIN
|
2005-06-22 02:47:54 +00:00
|
|
|
#endif
|
|
|
|
|
2003-06-29 16:33:04 +00:00
|
|
|
MEMORY
|
|
|
|
{
|
2005-06-28 21:12:11 +00:00
|
|
|
PLUGIN_RAM : ORIGIN = THIS_ORIGIN, LENGTH = THIS_LENGTH
|
2008-05-10 22:03:45 +00:00
|
|
|
#if defined(IRAMSIZE) && IRAMSIZE != 0
|
2005-02-22 00:42:22 +00:00
|
|
|
PLUGIN_IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
|
|
|
|
#endif
|
2003-06-29 16:33:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SECTIONS
|
|
|
|
{
|
2006-01-15 18:20:18 +00:00
|
|
|
.header : {
|
|
|
|
_plugin_start_addr = .;
|
|
|
|
plugin_start_addr = .;
|
|
|
|
KEEP(*(.header))
|
|
|
|
} > PLUGIN_RAM
|
|
|
|
|
|
|
|
.text :
|
2006-01-08 22:50:14 +00:00
|
|
|
{
|
2005-06-29 21:04:22 +00:00
|
|
|
*(.text*)
|
2008-05-10 22:03:45 +00:00
|
|
|
#if defined(IRAMSIZE) && IRAMSIZE == 0
|
2009-03-11 03:46:24 +00:00
|
|
|
*(.icode)
|
2008-05-10 22:03:45 +00:00
|
|
|
#endif
|
2006-12-29 02:49:12 +00:00
|
|
|
#ifdef CPU_ARM
|
2005-11-12 16:01:15 +00:00
|
|
|
*(.glue_7)
|
|
|
|
*(.glue_7t)
|
|
|
|
#endif
|
2003-06-29 16:33:04 +00:00
|
|
|
} > PLUGIN_RAM
|
|
|
|
|
2007-01-13 02:24:15 +00:00
|
|
|
.rodata :
|
2006-01-08 22:50:14 +00:00
|
|
|
{
|
2005-06-29 21:04:22 +00:00
|
|
|
*(.rodata*)
|
2008-05-10 22:03:45 +00:00
|
|
|
#if defined(IRAMSIZE) && IRAMSIZE == 0
|
2009-03-11 03:46:24 +00:00
|
|
|
*(.irodata)
|
2008-05-10 22:03:45 +00:00
|
|
|
#endif
|
2003-08-04 19:13:42 +00:00
|
|
|
. = ALIGN(0x4);
|
2006-01-08 22:50:14 +00:00
|
|
|
} > PLUGIN_RAM
|
|
|
|
|
2006-01-15 18:20:18 +00:00
|
|
|
.data :
|
2006-01-08 22:50:14 +00:00
|
|
|
{
|
|
|
|
*(.data*)
|
2008-05-10 22:03:45 +00:00
|
|
|
#if defined(IRAMSIZE) && IRAMSIZE == 0
|
2009-03-11 03:46:24 +00:00
|
|
|
*(.idata)
|
2008-05-10 22:03:45 +00:00
|
|
|
#endif
|
2008-04-06 04:34:57 +00:00
|
|
|
} > PLUGIN_RAM
|
|
|
|
|
|
|
|
#if NOCACHE_BASE != 0
|
|
|
|
.ncdata . + NOCACHE_BASE :
|
|
|
|
{
|
|
|
|
. = ALIGN(CACHEALIGN_SIZE);
|
|
|
|
*(.ncdata*)
|
|
|
|
. = ALIGN(CACHEALIGN_SIZE);
|
2009-11-20 07:38:57 +00:00
|
|
|
/* EABI currently needs iramcopy defined here, otherwise .iram can sometimes
|
|
|
|
have an incorrect load address, breaking codecs. */
|
2006-03-21 12:25:40 +00:00
|
|
|
#if defined(IRAMSIZE)
|
2009-11-20 07:38:57 +00:00
|
|
|
iramcopy = . - NOCACHE_BASE;
|
|
|
|
#endif
|
|
|
|
} AT> PLUGIN_RAM
|
|
|
|
/* This definition is used when NOCACHE_BASE is 0. The address offset bug only
|
|
|
|
seems to occur when the empty .ncdata is present. */
|
|
|
|
#elif defined(IRAMSIZE)
|
|
|
|
iramcopy = .;
|
2005-02-22 00:42:22 +00:00
|
|
|
#endif
|
|
|
|
|
2007-01-13 02:24:15 +00:00
|
|
|
/DISCARD/ :
|
2006-01-08 22:50:14 +00:00
|
|
|
{
|
|
|
|
*(.eh_frame)
|
2009-02-09 10:02:38 +00:00
|
|
|
#ifdef CPU_MIPS
|
|
|
|
*(.rel.dyn)
|
|
|
|
#endif
|
2006-01-08 22:50:14 +00:00
|
|
|
}
|
|
|
|
|
2008-05-10 22:03:45 +00:00
|
|
|
#if defined(IRAMSIZE) && IRAMSIZE != 0
|
2005-02-22 00:42:22 +00:00
|
|
|
.iram IRAMORIG : AT ( iramcopy)
|
|
|
|
{
|
|
|
|
iramstart = .;
|
|
|
|
*(.icode)
|
2005-10-19 19:35:24 +00:00
|
|
|
*(.irodata)
|
2005-02-22 00:42:22 +00:00
|
|
|
*(.idata)
|
|
|
|
iramend = .;
|
|
|
|
} > PLUGIN_IRAM
|
2006-01-08 22:50:14 +00:00
|
|
|
|
2008-04-06 04:34:57 +00:00
|
|
|
|
2006-01-08 22:50:14 +00:00
|
|
|
.ibss (NOLOAD) :
|
|
|
|
{
|
|
|
|
iedata = .;
|
|
|
|
*(.ibss)
|
|
|
|
. = ALIGN(0x4);
|
|
|
|
iend = .;
|
|
|
|
} > PLUGIN_IRAM
|
2005-02-22 00:42:22 +00:00
|
|
|
#endif
|
2006-11-26 18:31:41 +00:00
|
|
|
|
|
|
|
.bss (NOLOAD) :
|
2006-01-08 22:50:14 +00:00
|
|
|
{
|
2008-04-06 04:34:57 +00:00
|
|
|
plugin_bss_start = .;
|
2006-01-08 22:50:14 +00:00
|
|
|
*(.bss*)
|
2008-05-10 22:03:45 +00:00
|
|
|
#if defined(IRAMSIZE) && IRAMSIZE == 0
|
2009-03-11 03:46:24 +00:00
|
|
|
*(.ibss)
|
2008-05-10 22:03:45 +00:00
|
|
|
#endif
|
2006-01-08 23:45:29 +00:00
|
|
|
*(COMMON)
|
2006-01-15 18:20:18 +00:00
|
|
|
. = ALIGN(0x4);
|
2008-04-06 04:34:57 +00:00
|
|
|
} > PLUGIN_RAM
|
|
|
|
|
|
|
|
#if NOCACHE_BASE != 0
|
|
|
|
.ncbss . + NOCACHE_BASE (NOLOAD) :
|
|
|
|
{
|
|
|
|
. = ALIGN(CACHEALIGN_SIZE);
|
|
|
|
*(.ncbss*)
|
|
|
|
. = ALIGN(CACHEALIGN_SIZE);
|
|
|
|
} AT> PLUGIN_RAM
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Restore . */
|
|
|
|
.pluginend . - NOCACHE_BASE :
|
|
|
|
{
|
2006-01-15 18:20:18 +00:00
|
|
|
_plugin_end_addr = .;
|
|
|
|
plugin_end_addr = .;
|
2008-04-06 04:34:57 +00:00
|
|
|
}
|
2006-01-08 22:50:14 +00:00
|
|
|
|
2005-06-29 21:04:22 +00:00
|
|
|
/* Special trick to avoid a linker error when no other sections are
|
|
|
|
left after garbage collection (plugin not for this platform) */
|
2007-01-13 02:24:15 +00:00
|
|
|
.comment 0 :
|
2006-01-08 22:50:14 +00:00
|
|
|
{
|
2005-06-29 21:04:22 +00:00
|
|
|
KEEP(*(.comment))
|
|
|
|
}
|
2003-06-29 16:33:04 +00:00
|
|
|
}
|