2008-06-27 23:24:34 +00:00
|
|
|
/***************************************************************************
|
|
|
|
* __________ __ ___.
|
|
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
|
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
|
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
|
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
|
|
|
* \/ \/ \/ \/ \/
|
|
|
|
* $Id$
|
|
|
|
*
|
|
|
|
* Copyright (C) 2008 by Marcoen Hirschberg
|
|
|
|
*
|
2008-06-28 18:10:04 +00:00
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License
|
|
|
|
* as published by the Free Software Foundation; either version 2
|
|
|
|
* of the License, or (at your option) any later version.
|
2008-06-27 23:24:34 +00:00
|
|
|
*
|
|
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
|
|
|
* KIND, either express or implied.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
#include "config.h"
|
|
|
|
#include "cpu.h"
|
|
|
|
|
|
|
|
.section .init.text,"ax",%progbits
|
|
|
|
|
|
|
|
.global start
|
|
|
|
start:
|
|
|
|
/* Exception vectors */
|
2010-06-18 18:31:14 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* reset vector *MUST* use relative-addressing only
|
|
|
|
* the MMU might not be enabled yet, and the PC might point to
|
|
|
|
* a memory region not present in the linked binary
|
|
|
|
*/
|
|
|
|
|
2010-06-18 17:33:51 +00:00
|
|
|
b newstart
|
|
|
|
b undef_instr_handler
|
|
|
|
b software_int_handler
|
|
|
|
b prefetch_abort_handler
|
|
|
|
b data_abort_handler
|
|
|
|
b reserved_handler
|
|
|
|
b irq_handler
|
|
|
|
b fiq_handler
|
2008-11-09 06:17:16 +00:00
|
|
|
|
2008-11-18 17:15:56 +00:00
|
|
|
_vectorsend:
|
2008-11-09 06:17:16 +00:00
|
|
|
|
|
|
|
.text
|
|
|
|
|
2008-06-27 23:24:34 +00:00
|
|
|
newstart:
|
|
|
|
msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
|
2008-11-09 06:17:16 +00:00
|
|
|
|
2010-06-18 17:33:51 +00:00
|
|
|
#if CONFIG_CPU == AS3525 || CONFIG_CPU == AS3525v2
|
|
|
|
bl memory_init
|
|
|
|
#endif
|
2008-11-18 17:15:56 +00:00
|
|
|
|
2010-06-18 17:33:51 +00:00
|
|
|
#ifdef USE_IRAM
|
2008-11-18 17:15:56 +00:00
|
|
|
/* Zero out IBSS */
|
|
|
|
ldr r2, =_iedata
|
|
|
|
ldr r3, =_iend
|
|
|
|
mov r4, #0
|
|
|
|
1:
|
|
|
|
cmp r3, r2
|
|
|
|
strhi r4, [r2], #4
|
|
|
|
bhi 1b
|
|
|
|
|
|
|
|
/* Copy the IRAM */
|
2010-03-03 23:20:32 +00:00
|
|
|
/* must be done before bss is zeroed */
|
2008-11-18 17:15:56 +00:00
|
|
|
ldr r2, =_iramcopy
|
|
|
|
ldr r3, =_iramstart
|
|
|
|
ldr r4, =_iramend
|
|
|
|
1:
|
|
|
|
cmp r4, r3
|
|
|
|
ldrhi r5, [r2], #4
|
|
|
|
strhi r5, [r3], #4
|
|
|
|
bhi 1b
|
2010-03-03 23:20:32 +00:00
|
|
|
#endif
|
|
|
|
|
2010-03-03 23:52:36 +00:00
|
|
|
#ifdef HAVE_INIT_ATTR
|
2010-03-03 23:20:32 +00:00
|
|
|
/* copy init data to codec buffer */
|
|
|
|
/* must be done before bss is zeroed */
|
|
|
|
ldr r2, =_initcopy
|
|
|
|
ldr r3, =_initstart
|
|
|
|
ldr r4, =_initend
|
|
|
|
1:
|
|
|
|
cmp r4, r3
|
|
|
|
ldrhi r5, [r2], #4
|
|
|
|
strhi r5, [r3], #4
|
|
|
|
bhi 1b
|
|
|
|
|
|
|
|
mov r2, #0
|
|
|
|
mcr p15, 0, r2, c7, c5, 0 @ Invalidate ICache
|
2008-11-09 06:17:16 +00:00
|
|
|
#endif
|
|
|
|
|
2008-06-27 23:24:34 +00:00
|
|
|
/* Initialise bss section to zero */
|
|
|
|
ldr r2, =_edata
|
|
|
|
ldr r3, =_end
|
|
|
|
mov r4, #0
|
|
|
|
1:
|
|
|
|
cmp r3, r2
|
|
|
|
strhi r4, [r2], #4
|
|
|
|
bhi 1b
|
2010-03-03 23:20:32 +00:00
|
|
|
|
2008-06-27 23:24:34 +00:00
|
|
|
/* Set up stack for IRQ mode */
|
|
|
|
msr cpsr_c, #0xd2
|
|
|
|
ldr sp, =irq_stack
|
|
|
|
|
|
|
|
/* Set up stack for FIQ mode */
|
|
|
|
msr cpsr_c, #0xd1
|
|
|
|
ldr sp, =fiq_stack
|
|
|
|
|
2011-10-11 16:06:03 +00:00
|
|
|
/* Let svc, abort and undefined modes use irq stack */
|
|
|
|
msr cpsr_c, #0xd3
|
|
|
|
ldr sp, =irq_stack
|
2008-06-27 23:24:34 +00:00
|
|
|
msr cpsr_c, #0xd7
|
|
|
|
ldr sp, =irq_stack
|
|
|
|
msr cpsr_c, #0xdb
|
|
|
|
ldr sp, =irq_stack
|
|
|
|
|
2011-10-11 16:06:03 +00:00
|
|
|
/* Switch to sys mode */
|
|
|
|
msr cpsr_c, #0xdf
|
|
|
|
|
|
|
|
/* Set up some stack and munge it with 0xdeadbeef */
|
|
|
|
ldr sp, =stackend
|
|
|
|
ldr r2, =stackbegin
|
|
|
|
ldr r3, =0xdeadbeef
|
|
|
|
1:
|
|
|
|
cmp sp, r2
|
|
|
|
strhi r3, [r2], #4
|
|
|
|
bhi 1b
|
|
|
|
|
2010-06-18 17:33:51 +00:00
|
|
|
ldr ip, =main @ make sure we are using the virtual address
|
|
|
|
bx ip
|
2008-06-27 23:24:34 +00:00
|
|
|
|
|
|
|
/* All illegal exceptions call into UIE with exception address as first
|
|
|
|
* parameter. This is calculated differently depending on which exception
|
|
|
|
* we're in. Second parameter is exception number, used for a string lookup
|
|
|
|
* in UIE. */
|
|
|
|
undef_instr_handler:
|
2010-06-12 16:55:51 +00:00
|
|
|
sub r0, lr, #4 @ r0 points to the faulty ARM instruction
|
|
|
|
#ifdef USE_THUMB
|
|
|
|
mrs r1, spsr
|
|
|
|
tst r1, #(1<<5) @ T bit set ?
|
|
|
|
subne r0, lr, #2 @ if yes, r0 points to the faulty THUMB instruction
|
|
|
|
#endif /* USE_THUMB */
|
2008-06-27 23:24:34 +00:00
|
|
|
mov r1, #0
|
|
|
|
b UIE
|
|
|
|
|
2011-10-11 16:06:03 +00:00
|
|
|
/* We run sys mode most of the time, and should never see a software
|
|
|
|
* exception being thrown. Make it illegal and call UIE. */
|
2008-06-27 23:24:34 +00:00
|
|
|
software_int_handler:
|
|
|
|
reserved_handler:
|
2011-10-11 16:06:03 +00:00
|
|
|
sub r0, lr, #4
|
|
|
|
mov r1, #4
|
|
|
|
b UIE
|
2008-06-27 23:24:34 +00:00
|
|
|
|
|
|
|
prefetch_abort_handler:
|
|
|
|
sub r0, lr, #4
|
|
|
|
mov r1, #1
|
|
|
|
b UIE
|
|
|
|
|
|
|
|
data_abort_handler:
|
|
|
|
sub r0, lr, #8
|
|
|
|
mov r1, #2
|
|
|
|
b UIE
|
|
|
|
|
|
|
|
/* 256 words of IRQ stack */
|
|
|
|
.space 256*4
|
|
|
|
irq_stack:
|
|
|
|
|
|
|
|
/* 256 words of FIQ stack */
|
|
|
|
.space 256*4
|
|
|
|
fiq_stack:
|
|
|
|
end:
|