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rockbox/firmware/target/arm/imx233/regs/stmp3600/hwecc.h

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imx233: generate register headers using headergen_v2 and update code for it NOTE: this commit does not introduce any change, ideally even the binary should be almost the same. I checked the disassembly by hand and there are only a few differences here and there, mostly the compiler decides to compile very close expressions slightly differently. I tried to run the new code on several targets to make sure and saw no difference. The major syntax changes of the new headers are as follows: - BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once: BF_WR(reg, field1(value1), field2(value2), ...) - BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW - there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply BF_WR with field_V(name) - the old BF_SETV macro has no trivial equivalent and is replaced with its its equivalent for BF_WR(reg_SET, ...) I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the redundant "regs". Final note: the registers were generated using the following command: ./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stmp3600 version: 2.4.0
* stmp3600 authors: Amaury Pouly
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_STMP3600_HWECC_H__
#define __HEADERGEN_STMP3600_HWECC_H__
#define HW_HWECC_CTRL HW(HWECC_CTRL)
#define HWA_HWECC_CTRL (0x80008000 + 0x0)
#define HWT_HWECC_CTRL HWIO_32_RW
#define HWN_HWECC_CTRL HWECC_CTRL
#define HWI_HWECC_CTRL
#define HW_HWECC_CTRL_SET HW(HWECC_CTRL_SET)
#define HWA_HWECC_CTRL_SET (HWA_HWECC_CTRL + 0x4)
#define HWT_HWECC_CTRL_SET HWIO_32_WO
#define HWN_HWECC_CTRL_SET HWECC_CTRL
#define HWI_HWECC_CTRL_SET
#define HW_HWECC_CTRL_CLR HW(HWECC_CTRL_CLR)
#define HWA_HWECC_CTRL_CLR (HWA_HWECC_CTRL + 0x8)
#define HWT_HWECC_CTRL_CLR HWIO_32_WO
#define HWN_HWECC_CTRL_CLR HWECC_CTRL
#define HWI_HWECC_CTRL_CLR
#define HW_HWECC_CTRL_TOG HW(HWECC_CTRL_TOG)
#define HWA_HWECC_CTRL_TOG (HWA_HWECC_CTRL + 0xc)
#define HWT_HWECC_CTRL_TOG HWIO_32_WO
#define HWN_HWECC_CTRL_TOG HWECC_CTRL
#define HWI_HWECC_CTRL_TOG
#define BP_HWECC_CTRL_SFTRST 31
#define BM_HWECC_CTRL_SFTRST 0x80000000
#define BF_HWECC_CTRL_SFTRST(v) (((v) & 0x1) << 31)
#define BFM_HWECC_CTRL_SFTRST(v) BM_HWECC_CTRL_SFTRST
#define BF_HWECC_CTRL_SFTRST_V(e) BF_HWECC_CTRL_SFTRST(BV_HWECC_CTRL_SFTRST__##e)
#define BFM_HWECC_CTRL_SFTRST_V(v) BM_HWECC_CTRL_SFTRST
#define BP_HWECC_CTRL_CLKGATE 30
#define BM_HWECC_CTRL_CLKGATE 0x40000000
#define BF_HWECC_CTRL_CLKGATE(v) (((v) & 0x1) << 30)
#define BFM_HWECC_CTRL_CLKGATE(v) BM_HWECC_CTRL_CLKGATE
#define BF_HWECC_CTRL_CLKGATE_V(e) BF_HWECC_CTRL_CLKGATE(BV_HWECC_CTRL_CLKGATE__##e)
#define BFM_HWECC_CTRL_CLKGATE_V(v) BM_HWECC_CTRL_CLKGATE
#define BP_HWECC_CTRL_NUM_SYMBOLS 16
#define BM_HWECC_CTRL_NUM_SYMBOLS 0x1ff0000
#define BF_HWECC_CTRL_NUM_SYMBOLS(v) (((v) & 0x1ff) << 16)
#define BFM_HWECC_CTRL_NUM_SYMBOLS(v) BM_HWECC_CTRL_NUM_SYMBOLS
#define BF_HWECC_CTRL_NUM_SYMBOLS_V(e) BF_HWECC_CTRL_NUM_SYMBOLS(BV_HWECC_CTRL_NUM_SYMBOLS__##e)
#define BFM_HWECC_CTRL_NUM_SYMBOLS_V(v) BM_HWECC_CTRL_NUM_SYMBOLS
#define BP_HWECC_CTRL_DMAWAIT_COUNT 8
#define BM_HWECC_CTRL_DMAWAIT_COUNT 0x1f00
#define BF_HWECC_CTRL_DMAWAIT_COUNT(v) (((v) & 0x1f) << 8)
#define BFM_HWECC_CTRL_DMAWAIT_COUNT(v) BM_HWECC_CTRL_DMAWAIT_COUNT
#define BF_HWECC_CTRL_DMAWAIT_COUNT_V(e) BF_HWECC_CTRL_DMAWAIT_COUNT(BV_HWECC_CTRL_DMAWAIT_COUNT__##e)
#define BFM_HWECC_CTRL_DMAWAIT_COUNT_V(v) BM_HWECC_CTRL_DMAWAIT_COUNT
#define BP_HWECC_CTRL_BYTE_ENABLE 6
#define BM_HWECC_CTRL_BYTE_ENABLE 0x40
#define BF_HWECC_CTRL_BYTE_ENABLE(v) (((v) & 0x1) << 6)
#define BFM_HWECC_CTRL_BYTE_ENABLE(v) BM_HWECC_CTRL_BYTE_ENABLE
#define BF_HWECC_CTRL_BYTE_ENABLE_V(e) BF_HWECC_CTRL_BYTE_ENABLE(BV_HWECC_CTRL_BYTE_ENABLE__##e)
#define BFM_HWECC_CTRL_BYTE_ENABLE_V(v) BM_HWECC_CTRL_BYTE_ENABLE
#define BP_HWECC_CTRL_ECC_SEL 5
#define BM_HWECC_CTRL_ECC_SEL 0x20
#define BF_HWECC_CTRL_ECC_SEL(v) (((v) & 0x1) << 5)
#define BFM_HWECC_CTRL_ECC_SEL(v) BM_HWECC_CTRL_ECC_SEL
#define BF_HWECC_CTRL_ECC_SEL_V(e) BF_HWECC_CTRL_ECC_SEL(BV_HWECC_CTRL_ECC_SEL__##e)
#define BFM_HWECC_CTRL_ECC_SEL_V(v) BM_HWECC_CTRL_ECC_SEL
#define BP_HWECC_CTRL_ENC_SEL 4
#define BM_HWECC_CTRL_ENC_SEL 0x10
#define BF_HWECC_CTRL_ENC_SEL(v) (((v) & 0x1) << 4)
#define BFM_HWECC_CTRL_ENC_SEL(v) BM_HWECC_CTRL_ENC_SEL
#define BF_HWECC_CTRL_ENC_SEL_V(e) BF_HWECC_CTRL_ENC_SEL(BV_HWECC_CTRL_ENC_SEL__##e)
#define BFM_HWECC_CTRL_ENC_SEL_V(v) BM_HWECC_CTRL_ENC_SEL
#define BP_HWECC_CTRL_UNCORR_IRQ 2
#define BM_HWECC_CTRL_UNCORR_IRQ 0x4
#define BF_HWECC_CTRL_UNCORR_IRQ(v) (((v) & 0x1) << 2)
#define BFM_HWECC_CTRL_UNCORR_IRQ(v) BM_HWECC_CTRL_UNCORR_IRQ
#define BF_HWECC_CTRL_UNCORR_IRQ_V(e) BF_HWECC_CTRL_UNCORR_IRQ(BV_HWECC_CTRL_UNCORR_IRQ__##e)
#define BFM_HWECC_CTRL_UNCORR_IRQ_V(v) BM_HWECC_CTRL_UNCORR_IRQ
#define BP_HWECC_CTRL_UNCORR_IRQ_EN 1
#define BM_HWECC_CTRL_UNCORR_IRQ_EN 0x2
#define BF_HWECC_CTRL_UNCORR_IRQ_EN(v) (((v) & 0x1) << 1)
#define BFM_HWECC_CTRL_UNCORR_IRQ_EN(v) BM_HWECC_CTRL_UNCORR_IRQ_EN
#define BF_HWECC_CTRL_UNCORR_IRQ_EN_V(e) BF_HWECC_CTRL_UNCORR_IRQ_EN(BV_HWECC_CTRL_UNCORR_IRQ_EN__##e)
#define BFM_HWECC_CTRL_UNCORR_IRQ_EN_V(v) BM_HWECC_CTRL_UNCORR_IRQ_EN
#define BP_HWECC_CTRL_RUN 0
#define BM_HWECC_CTRL_RUN 0x1
#define BF_HWECC_CTRL_RUN(v) (((v) & 0x1) << 0)
#define BFM_HWECC_CTRL_RUN(v) BM_HWECC_CTRL_RUN
#define BF_HWECC_CTRL_RUN_V(e) BF_HWECC_CTRL_RUN(BV_HWECC_CTRL_RUN__##e)
#define BFM_HWECC_CTRL_RUN_V(v) BM_HWECC_CTRL_RUN
#define HW_HWECC_STAT HW(HWECC_STAT)
#define HWA_HWECC_STAT (0x80008000 + 0x10)
#define HWT_HWECC_STAT HWIO_32_RW
#define HWN_HWECC_STAT HWECC_STAT
#define HWI_HWECC_STAT
#define BP_HWECC_STAT_RSDEC_PRESENT 31
#define BM_HWECC_STAT_RSDEC_PRESENT 0x80000000
#define BF_HWECC_STAT_RSDEC_PRESENT(v) (((v) & 0x1) << 31)
#define BFM_HWECC_STAT_RSDEC_PRESENT(v) BM_HWECC_STAT_RSDEC_PRESENT
#define BF_HWECC_STAT_RSDEC_PRESENT_V(e) BF_HWECC_STAT_RSDEC_PRESENT(BV_HWECC_STAT_RSDEC_PRESENT__##e)
#define BFM_HWECC_STAT_RSDEC_PRESENT_V(v) BM_HWECC_STAT_RSDEC_PRESENT
#define BP_HWECC_STAT_RSENC_PRESENT 30
#define BM_HWECC_STAT_RSENC_PRESENT 0x40000000
#define BF_HWECC_STAT_RSENC_PRESENT(v) (((v) & 0x1) << 30)
#define BFM_HWECC_STAT_RSENC_PRESENT(v) BM_HWECC_STAT_RSENC_PRESENT
#define BF_HWECC_STAT_RSENC_PRESENT_V(e) BF_HWECC_STAT_RSENC_PRESENT(BV_HWECC_STAT_RSENC_PRESENT__##e)
#define BFM_HWECC_STAT_RSENC_PRESENT_V(v) BM_HWECC_STAT_RSENC_PRESENT
#define BP_HWECC_STAT_SSDEC_PRESENT 29
#define BM_HWECC_STAT_SSDEC_PRESENT 0x20000000
#define BF_HWECC_STAT_SSDEC_PRESENT(v) (((v) & 0x1) << 29)
#define BFM_HWECC_STAT_SSDEC_PRESENT(v) BM_HWECC_STAT_SSDEC_PRESENT
#define BF_HWECC_STAT_SSDEC_PRESENT_V(e) BF_HWECC_STAT_SSDEC_PRESENT(BV_HWECC_STAT_SSDEC_PRESENT__##e)
#define BFM_HWECC_STAT_SSDEC_PRESENT_V(v) BM_HWECC_STAT_SSDEC_PRESENT
#define BP_HWECC_STAT_SSENC_PRESENT 28
#define BM_HWECC_STAT_SSENC_PRESENT 0x10000000
#define BF_HWECC_STAT_SSENC_PRESENT(v) (((v) & 0x1) << 28)
#define BFM_HWECC_STAT_SSENC_PRESENT(v) BM_HWECC_STAT_SSENC_PRESENT
#define BF_HWECC_STAT_SSENC_PRESENT_V(e) BF_HWECC_STAT_SSENC_PRESENT(BV_HWECC_STAT_SSENC_PRESENT__##e)
#define BFM_HWECC_STAT_SSENC_PRESENT_V(v) BM_HWECC_STAT_SSENC_PRESENT
#define HW_HWECC_DEBUG0 HW(HWECC_DEBUG0)
#define HWA_HWECC_DEBUG0 (0x80008000 + 0x20)
#define HWT_HWECC_DEBUG0 HWIO_32_RW
#define HWN_HWECC_DEBUG0 HWECC_DEBUG0
#define HWI_HWECC_DEBUG0
#define BP_HWECC_DEBUG0_DMA_PENDCMD 29
#define BM_HWECC_DEBUG0_DMA_PENDCMD 0x20000000
#define BF_HWECC_DEBUG0_DMA_PENDCMD(v) (((v) & 0x1) << 29)
#define BFM_HWECC_DEBUG0_DMA_PENDCMD(v) BM_HWECC_DEBUG0_DMA_PENDCMD
#define BF_HWECC_DEBUG0_DMA_PENDCMD_V(e) BF_HWECC_DEBUG0_DMA_PENDCMD(BV_HWECC_DEBUG0_DMA_PENDCMD__##e)
#define BFM_HWECC_DEBUG0_DMA_PENDCMD_V(v) BM_HWECC_DEBUG0_DMA_PENDCMD
#define BP_HWECC_DEBUG0_DMA_PREQ 28
#define BM_HWECC_DEBUG0_DMA_PREQ 0x10000000
#define BF_HWECC_DEBUG0_DMA_PREQ(v) (((v) & 0x1) << 28)
#define BFM_HWECC_DEBUG0_DMA_PREQ(v) BM_HWECC_DEBUG0_DMA_PREQ
#define BF_HWECC_DEBUG0_DMA_PREQ_V(e) BF_HWECC_DEBUG0_DMA_PREQ(BV_HWECC_DEBUG0_DMA_PREQ__##e)
#define BFM_HWECC_DEBUG0_DMA_PREQ_V(v) BM_HWECC_DEBUG0_DMA_PREQ
#define BP_HWECC_DEBUG0_SYMBOL_STATE 24
#define BM_HWECC_DEBUG0_SYMBOL_STATE 0xf000000
#define BF_HWECC_DEBUG0_SYMBOL_STATE(v) (((v) & 0xf) << 24)
#define BFM_HWECC_DEBUG0_SYMBOL_STATE(v) BM_HWECC_DEBUG0_SYMBOL_STATE
#define BF_HWECC_DEBUG0_SYMBOL_STATE_V(e) BF_HWECC_DEBUG0_SYMBOL_STATE(BV_HWECC_DEBUG0_SYMBOL_STATE__##e)
#define BFM_HWECC_DEBUG0_SYMBOL_STATE_V(v) BM_HWECC_DEBUG0_SYMBOL_STATE
#define BP_HWECC_DEBUG0_CTRL_STATE 16
#define BM_HWECC_DEBUG0_CTRL_STATE 0x3f0000
#define BF_HWECC_DEBUG0_CTRL_STATE(v) (((v) & 0x3f) << 16)
#define BFM_HWECC_DEBUG0_CTRL_STATE(v) BM_HWECC_DEBUG0_CTRL_STATE
#define BF_HWECC_DEBUG0_CTRL_STATE_V(e) BF_HWECC_DEBUG0_CTRL_STATE(BV_HWECC_DEBUG0_CTRL_STATE__##e)
#define BFM_HWECC_DEBUG0_CTRL_STATE_V(v) BM_HWECC_DEBUG0_CTRL_STATE
#define BP_HWECC_DEBUG0_ECC_EXCEPTION 12
#define BM_HWECC_DEBUG0_ECC_EXCEPTION 0xf000
#define BF_HWECC_DEBUG0_ECC_EXCEPTION(v) (((v) & 0xf) << 12)
#define BFM_HWECC_DEBUG0_ECC_EXCEPTION(v) BM_HWECC_DEBUG0_ECC_EXCEPTION
#define BF_HWECC_DEBUG0_ECC_EXCEPTION_V(e) BF_HWECC_DEBUG0_ECC_EXCEPTION(BV_HWECC_DEBUG0_ECC_EXCEPTION__##e)
#define BFM_HWECC_DEBUG0_ECC_EXCEPTION_V(v) BM_HWECC_DEBUG0_ECC_EXCEPTION
#define BP_HWECC_DEBUG0_NUM_BIT_ERRORS 4
#define BM_HWECC_DEBUG0_NUM_BIT_ERRORS 0x3f0
#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v) (((v) & 0x3f) << 4)
#define BFM_HWECC_DEBUG0_NUM_BIT_ERRORS(v) BM_HWECC_DEBUG0_NUM_BIT_ERRORS
#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS_V(e) BF_HWECC_DEBUG0_NUM_BIT_ERRORS(BV_HWECC_DEBUG0_NUM_BIT_ERRORS__##e)
#define BFM_HWECC_DEBUG0_NUM_BIT_ERRORS_V(v) BM_HWECC_DEBUG0_NUM_BIT_ERRORS
#define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0
#define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0x7
#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v) (((v) & 0x7) << 0)
#define BFM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v) BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS
#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS_V(e) BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(BV_HWECC_DEBUG0_NUM_SYMBOL_ERRORS__##e)
#define BFM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS_V(v) BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS
#define HW_HWECC_DEBUG1 HW(HWECC_DEBUG1)
#define HWA_HWECC_DEBUG1 (0x80008000 + 0x30)
#define HWT_HWECC_DEBUG1 HWIO_32_RW
#define HWN_HWECC_DEBUG1 HWECC_DEBUG1
#define HWI_HWECC_DEBUG1
#define BP_HWECC_DEBUG1_SYNDROME2 18
#define BM_HWECC_DEBUG1_SYNDROME2 0x7fc0000
#define BF_HWECC_DEBUG1_SYNDROME2(v) (((v) & 0x1ff) << 18)
#define BFM_HWECC_DEBUG1_SYNDROME2(v) BM_HWECC_DEBUG1_SYNDROME2
#define BF_HWECC_DEBUG1_SYNDROME2_V(e) BF_HWECC_DEBUG1_SYNDROME2(BV_HWECC_DEBUG1_SYNDROME2__##e)
#define BFM_HWECC_DEBUG1_SYNDROME2_V(v) BM_HWECC_DEBUG1_SYNDROME2
#define BP_HWECC_DEBUG1_SYNDROME1 9
#define BM_HWECC_DEBUG1_SYNDROME1 0x3fe00
#define BF_HWECC_DEBUG1_SYNDROME1(v) (((v) & 0x1ff) << 9)
#define BFM_HWECC_DEBUG1_SYNDROME1(v) BM_HWECC_DEBUG1_SYNDROME1
#define BF_HWECC_DEBUG1_SYNDROME1_V(e) BF_HWECC_DEBUG1_SYNDROME1(BV_HWECC_DEBUG1_SYNDROME1__##e)
#define BFM_HWECC_DEBUG1_SYNDROME1_V(v) BM_HWECC_DEBUG1_SYNDROME1
#define BP_HWECC_DEBUG1_SYNDROME0 0
#define BM_HWECC_DEBUG1_SYNDROME0 0x1ff
#define BF_HWECC_DEBUG1_SYNDROME0(v) (((v) & 0x1ff) << 0)
#define BFM_HWECC_DEBUG1_SYNDROME0(v) BM_HWECC_DEBUG1_SYNDROME0
#define BF_HWECC_DEBUG1_SYNDROME0_V(e) BF_HWECC_DEBUG1_SYNDROME0(BV_HWECC_DEBUG1_SYNDROME0__##e)
#define BFM_HWECC_DEBUG1_SYNDROME0_V(v) BM_HWECC_DEBUG1_SYNDROME0
#define HW_HWECC_DEBUG2 HW(HWECC_DEBUG2)
#define HWA_HWECC_DEBUG2 (0x80008000 + 0x40)
#define HWT_HWECC_DEBUG2 HWIO_32_RW
#define HWN_HWECC_DEBUG2 HWECC_DEBUG2
#define HWI_HWECC_DEBUG2
#define BP_HWECC_DEBUG2_SYNDROME5 18
#define BM_HWECC_DEBUG2_SYNDROME5 0x7fc0000
#define BF_HWECC_DEBUG2_SYNDROME5(v) (((v) & 0x1ff) << 18)
#define BFM_HWECC_DEBUG2_SYNDROME5(v) BM_HWECC_DEBUG2_SYNDROME5
#define BF_HWECC_DEBUG2_SYNDROME5_V(e) BF_HWECC_DEBUG2_SYNDROME5(BV_HWECC_DEBUG2_SYNDROME5__##e)
#define BFM_HWECC_DEBUG2_SYNDROME5_V(v) BM_HWECC_DEBUG2_SYNDROME5
#define BP_HWECC_DEBUG2_SYNDROME4 9
#define BM_HWECC_DEBUG2_SYNDROME4 0x3fe00
#define BF_HWECC_DEBUG2_SYNDROME4(v) (((v) & 0x1ff) << 9)
#define BFM_HWECC_DEBUG2_SYNDROME4(v) BM_HWECC_DEBUG2_SYNDROME4
#define BF_HWECC_DEBUG2_SYNDROME4_V(e) BF_HWECC_DEBUG2_SYNDROME4(BV_HWECC_DEBUG2_SYNDROME4__##e)
#define BFM_HWECC_DEBUG2_SYNDROME4_V(v) BM_HWECC_DEBUG2_SYNDROME4
#define BP_HWECC_DEBUG2_SYNDROME3 0
#define BM_HWECC_DEBUG2_SYNDROME3 0x1ff
#define BF_HWECC_DEBUG2_SYNDROME3(v) (((v) & 0x1ff) << 0)
#define BFM_HWECC_DEBUG2_SYNDROME3(v) BM_HWECC_DEBUG2_SYNDROME3
#define BF_HWECC_DEBUG2_SYNDROME3_V(e) BF_HWECC_DEBUG2_SYNDROME3(BV_HWECC_DEBUG2_SYNDROME3__##e)
#define BFM_HWECC_DEBUG2_SYNDROME3_V(v) BM_HWECC_DEBUG2_SYNDROME3
#define HW_HWECC_DEBUG3 HW(HWECC_DEBUG3)
#define HWA_HWECC_DEBUG3 (0x80008000 + 0x50)
#define HWT_HWECC_DEBUG3 HWIO_32_RW
#define HWN_HWECC_DEBUG3 HWECC_DEBUG3
#define HWI_HWECC_DEBUG3
#define BP_HWECC_DEBUG3_OMEGA0 18
#define BM_HWECC_DEBUG3_OMEGA0 0x7fc0000
#define BF_HWECC_DEBUG3_OMEGA0(v) (((v) & 0x1ff) << 18)
#define BFM_HWECC_DEBUG3_OMEGA0(v) BM_HWECC_DEBUG3_OMEGA0
#define BF_HWECC_DEBUG3_OMEGA0_V(e) BF_HWECC_DEBUG3_OMEGA0(BV_HWECC_DEBUG3_OMEGA0__##e)
#define BFM_HWECC_DEBUG3_OMEGA0_V(v) BM_HWECC_DEBUG3_OMEGA0
#define BP_HWECC_DEBUG3_SYNDROME7 9
#define BM_HWECC_DEBUG3_SYNDROME7 0x3fe00
#define BF_HWECC_DEBUG3_SYNDROME7(v) (((v) & 0x1ff) << 9)
#define BFM_HWECC_DEBUG3_SYNDROME7(v) BM_HWECC_DEBUG3_SYNDROME7
#define BF_HWECC_DEBUG3_SYNDROME7_V(e) BF_HWECC_DEBUG3_SYNDROME7(BV_HWECC_DEBUG3_SYNDROME7__##e)
#define BFM_HWECC_DEBUG3_SYNDROME7_V(v) BM_HWECC_DEBUG3_SYNDROME7
#define BP_HWECC_DEBUG3_SYNDROME6 0
#define BM_HWECC_DEBUG3_SYNDROME6 0x1ff
#define BF_HWECC_DEBUG3_SYNDROME6(v) (((v) & 0x1ff) << 0)
#define BFM_HWECC_DEBUG3_SYNDROME6(v) BM_HWECC_DEBUG3_SYNDROME6
#define BF_HWECC_DEBUG3_SYNDROME6_V(e) BF_HWECC_DEBUG3_SYNDROME6(BV_HWECC_DEBUG3_SYNDROME6__##e)
#define BFM_HWECC_DEBUG3_SYNDROME6_V(v) BM_HWECC_DEBUG3_SYNDROME6
#define HW_HWECC_DEBUG4 HW(HWECC_DEBUG4)
#define HWA_HWECC_DEBUG4 (0x80008000 + 0x60)
#define HWT_HWECC_DEBUG4 HWIO_32_RW
#define HWN_HWECC_DEBUG4 HWECC_DEBUG4
#define HWI_HWECC_DEBUG4
#define BP_HWECC_DEBUG4_OMEGA3 18
#define BM_HWECC_DEBUG4_OMEGA3 0x7fc0000
#define BF_HWECC_DEBUG4_OMEGA3(v) (((v) & 0x1ff) << 18)
#define BFM_HWECC_DEBUG4_OMEGA3(v) BM_HWECC_DEBUG4_OMEGA3
#define BF_HWECC_DEBUG4_OMEGA3_V(e) BF_HWECC_DEBUG4_OMEGA3(BV_HWECC_DEBUG4_OMEGA3__##e)
#define BFM_HWECC_DEBUG4_OMEGA3_V(v) BM_HWECC_DEBUG4_OMEGA3
#define BP_HWECC_DEBUG4_OMEGA2 9
#define BM_HWECC_DEBUG4_OMEGA2 0x3fe00
#define BF_HWECC_DEBUG4_OMEGA2(v) (((v) & 0x1ff) << 9)
#define BFM_HWECC_DEBUG4_OMEGA2(v) BM_HWECC_DEBUG4_OMEGA2
#define BF_HWECC_DEBUG4_OMEGA2_V(e) BF_HWECC_DEBUG4_OMEGA2(BV_HWECC_DEBUG4_OMEGA2__##e)
#define BFM_HWECC_DEBUG4_OMEGA2_V(v) BM_HWECC_DEBUG4_OMEGA2
#define BP_HWECC_DEBUG4_OMEGA1 0
#define BM_HWECC_DEBUG4_OMEGA1 0x1ff
#define BF_HWECC_DEBUG4_OMEGA1(v) (((v) & 0x1ff) << 0)
#define BFM_HWECC_DEBUG4_OMEGA1(v) BM_HWECC_DEBUG4_OMEGA1
#define BF_HWECC_DEBUG4_OMEGA1_V(e) BF_HWECC_DEBUG4_OMEGA1(BV_HWECC_DEBUG4_OMEGA1__##e)
#define BFM_HWECC_DEBUG4_OMEGA1_V(v) BM_HWECC_DEBUG4_OMEGA1
#define HW_HWECC_DEBUG5 HW(HWECC_DEBUG5)
#define HWA_HWECC_DEBUG5 (0x80008000 + 0x70)
#define HWT_HWECC_DEBUG5 HWIO_32_RW
#define HWN_HWECC_DEBUG5 HWECC_DEBUG5
#define HWI_HWECC_DEBUG5
#define BP_HWECC_DEBUG5_LAMBDA2 18
#define BM_HWECC_DEBUG5_LAMBDA2 0x7fc0000
#define BF_HWECC_DEBUG5_LAMBDA2(v) (((v) & 0x1ff) << 18)
#define BFM_HWECC_DEBUG5_LAMBDA2(v) BM_HWECC_DEBUG5_LAMBDA2
#define BF_HWECC_DEBUG5_LAMBDA2_V(e) BF_HWECC_DEBUG5_LAMBDA2(BV_HWECC_DEBUG5_LAMBDA2__##e)
#define BFM_HWECC_DEBUG5_LAMBDA2_V(v) BM_HWECC_DEBUG5_LAMBDA2
#define BP_HWECC_DEBUG5_LAMBDA1 9
#define BM_HWECC_DEBUG5_LAMBDA1 0x3fe00
#define BF_HWECC_DEBUG5_LAMBDA1(v) (((v) & 0x1ff) << 9)
#define BFM_HWECC_DEBUG5_LAMBDA1(v) BM_HWECC_DEBUG5_LAMBDA1
#define BF_HWECC_DEBUG5_LAMBDA1_V(e) BF_HWECC_DEBUG5_LAMBDA1(BV_HWECC_DEBUG5_LAMBDA1__##e)
#define BFM_HWECC_DEBUG5_LAMBDA1_V(v) BM_HWECC_DEBUG5_LAMBDA1
#define BP_HWECC_DEBUG5_LAMBDA0 0
#define BM_HWECC_DEBUG5_LAMBDA0 0x1ff
#define BF_HWECC_DEBUG5_LAMBDA0(v) (((v) & 0x1ff) << 0)
#define BFM_HWECC_DEBUG5_LAMBDA0(v) BM_HWECC_DEBUG5_LAMBDA0
#define BF_HWECC_DEBUG5_LAMBDA0_V(e) BF_HWECC_DEBUG5_LAMBDA0(BV_HWECC_DEBUG5_LAMBDA0__##e)
#define BFM_HWECC_DEBUG5_LAMBDA0_V(v) BM_HWECC_DEBUG5_LAMBDA0
#define HW_HWECC_DEBUG6 HW(HWECC_DEBUG6)
#define HWA_HWECC_DEBUG6 (0x80008000 + 0x80)
#define HWT_HWECC_DEBUG6 HWIO_32_RW
#define HWN_HWECC_DEBUG6 HWECC_DEBUG6
#define HWI_HWECC_DEBUG6
#define BP_HWECC_DEBUG6_LAMBDA4 9
#define BM_HWECC_DEBUG6_LAMBDA4 0x3fe00
#define BF_HWECC_DEBUG6_LAMBDA4(v) (((v) & 0x1ff) << 9)
#define BFM_HWECC_DEBUG6_LAMBDA4(v) BM_HWECC_DEBUG6_LAMBDA4
#define BF_HWECC_DEBUG6_LAMBDA4_V(e) BF_HWECC_DEBUG6_LAMBDA4(BV_HWECC_DEBUG6_LAMBDA4__##e)
#define BFM_HWECC_DEBUG6_LAMBDA4_V(v) BM_HWECC_DEBUG6_LAMBDA4
#define BP_HWECC_DEBUG6_LAMBDA3 0
#define BM_HWECC_DEBUG6_LAMBDA3 0x1ff
#define BF_HWECC_DEBUG6_LAMBDA3(v) (((v) & 0x1ff) << 0)
#define BFM_HWECC_DEBUG6_LAMBDA3(v) BM_HWECC_DEBUG6_LAMBDA3
#define BF_HWECC_DEBUG6_LAMBDA3_V(e) BF_HWECC_DEBUG6_LAMBDA3(BV_HWECC_DEBUG6_LAMBDA3__##e)
#define BFM_HWECC_DEBUG6_LAMBDA3_V(v) BM_HWECC_DEBUG6_LAMBDA3
#define HW_HWECC_DATA HW(HWECC_DATA)
#define HWA_HWECC_DATA (0x80008000 + 0x90)
#define HWT_HWECC_DATA HWIO_32_RW
#define HWN_HWECC_DATA HWECC_DATA
#define HWI_HWECC_DATA
#define HW_HWECC_DATA_SET HW(HWECC_DATA_SET)
#define HWA_HWECC_DATA_SET (HWA_HWECC_DATA + 0x4)
#define HWT_HWECC_DATA_SET HWIO_32_WO
#define HWN_HWECC_DATA_SET HWECC_DATA
#define HWI_HWECC_DATA_SET
#define HW_HWECC_DATA_CLR HW(HWECC_DATA_CLR)
#define HWA_HWECC_DATA_CLR (HWA_HWECC_DATA + 0x8)
#define HWT_HWECC_DATA_CLR HWIO_32_WO
#define HWN_HWECC_DATA_CLR HWECC_DATA
#define HWI_HWECC_DATA_CLR
#define HW_HWECC_DATA_TOG HW(HWECC_DATA_TOG)
#define HWA_HWECC_DATA_TOG (HWA_HWECC_DATA + 0xc)
#define HWT_HWECC_DATA_TOG HWIO_32_WO
#define HWN_HWECC_DATA_TOG HWECC_DATA
#define HWI_HWECC_DATA_TOG
#define BP_HWECC_DATA_DATA 0
#define BM_HWECC_DATA_DATA 0xffffffff
#define BF_HWECC_DATA_DATA(v) (((v) & 0xffffffff) << 0)
#define BFM_HWECC_DATA_DATA(v) BM_HWECC_DATA_DATA
#define BF_HWECC_DATA_DATA_V(e) BF_HWECC_DATA_DATA(BV_HWECC_DATA_DATA__##e)
#define BFM_HWECC_DATA_DATA_V(v) BM_HWECC_DATA_DATA
#endif /* __HEADERGEN_STMP3600_HWECC_H__*/
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