2004-05-10 11:38:24 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Jens Arnold
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* Based on the work of Alan Korr and J<EFBFBD>rg Hohensohn
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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2004-10-26 06:53:34 +00:00
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#include "cpu.h"
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2004-05-10 11:38:24 +00:00
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2004-10-26 06:53:34 +00:00
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#if CONFIG_CPU == SH7034
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2004-05-10 11:38:24 +00:00
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#define LCDR (PBDR_ADDR+1)
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#ifdef HAVE_LCD_CHARCELLS
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#define LCD_DS 1 /* PB0 = 1 --- 0001 --- LCD-DS */
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#define LCD_CS 2 /* PB1 = 1 --- 0010 --- /LCD-CS */
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#define LCD_SD 4 /* PB2 = 1 --- 0100 --- LCD-SD */
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#define LCD_SC 8 /* PB3 = 1 --- 1000 --- LCD-SC */
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#else
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#define LCD_SD 1 /* PB0 = 1 --- 0001 */
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#define LCD_SC 2 /* PB1 = 1 --- 0010 */
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#define LCD_RS 4 /* PB2 = 1 --- 0100 */
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#define LCD_CS 8 /* PB3 = 1 --- 1000 */
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#define LCD_DS LCD_RS
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#endif
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/*
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* About /CS,DS,SC,SD
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* ------------------
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*
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* LCD on JBP and JBR uses a SPI protocol to receive orders (SDA and SCK lines)
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*
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* - /CS -> Chip Selection line :
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* 0 : LCD chipset is activated.
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* - DS -> Data Selection line, latched at the rising edge
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* of the 8th serial clock (*) :
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* 0 : instruction register,
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* 1 : data register;
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* - SC -> Serial Clock line (SDA).
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* - SD -> Serial Data line (SCK), latched at the rising edge
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* of each serial clock (*).
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*
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* _ _
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* /CS \ /
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* \______________________________________________________/
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* _____ ____ ____ ____ ____ ____ ____ ____ ____ _____
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* SD \/ D7 \/ D6 \/ D5 \/ D4 \/ D3 \/ D2 \/ D1 \/ D0 \/
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* _____/\____/\____/\____/\____/\____/\____/\____/\____/\_____
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*
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* _____ _ _ _ _ _ _ _ ________
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* SC \ * \ * \ * \ * \ * \ * \ * \ *
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* \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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* _ _________________________________________________________
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* DS \/
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* _/\_________________________________________________________
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*
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*/
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.section .icode,"ax",@progbits
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.align 2
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.global _lcd_write_command
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.type _lcd_write_command,@function
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/* Write a command byte to the lcd controller
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*
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* Arguments:
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* r4 - data byte (int)
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*
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* Register usage:
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* r0 - scratch
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* r1 - data byte (copied)
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* r2 - precalculated port value (CS, DS and SC low, SD high),
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* negated (neg)!
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* r3 - lcd port address
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* r5 - 1 (byte count for reuse of the loop in _lcd_write_data)
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*/
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_lcd_write_command:
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mov.l .lcdr,r3 /* put lcd data port address in r3 */
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mov r4,r1 /* copy data byte to r1 */
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mov #1,r5 /* set byte count to 1 (!) */
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/* This code will fail if an interrupt changes the contents of PBDRL.
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* If so, we must disable the interrupt here. */
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mov.b @r3,r0 /* r0 = PBDRL */
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or #(LCD_SD),r0 /* r0 |= LCD_SD */
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and #(~(LCD_CS|LCD_DS|LCD_SC)),r0 /* r0 &= ~(LCD_CS|LCD_DS|LCD_SC) */
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bra .single_transfer /* jump into the transfer loop */
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neg r0,r2 /* r2 = 0 - r0 */
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.align 2
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.global _lcd_write_data
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.type _lcd_write_data,@function
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/* A high performance function to write data to the display,
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* one or multiple bytes.
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*
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* Arguments:
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* r4 - data address
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* r5 - byte count
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*
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* Register usage:
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* r0 - scratch
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* r1 - current data byte
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* r2 - precalculated port value (CS and SC low, DS and SD high),
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* negated (neg)!
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* r3 - lcd port address
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*/
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_lcd_write_data:
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mov.l .lcdr,r3 /* put lcd data port address in r3 */
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nop /* align here */
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/* This code will fail if an interrupt changes the contents of PBDRL.
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* If so, we must disable the interrupt here. If disabling interrupts
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* for a long time (~9200 clks = ~830 <EFBFBD>s for transferring 112 bytes on
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* recorders)is undesirable, the loop has to be rewritten to
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* disable/precalculate/transfer/enable for each iteration. However,
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* this would significantly decrease performance. */
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mov.b @r3,r0 /* r0 = PBDRL */
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or #(LCD_DS|LCD_SD),r0 /* r0 |= LCD_DS|LCD_SD */
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and #(~(LCD_CS|LCD_SC)),r0 /* r0 &= ~(LCD_CS|LCD_SC) */
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neg r0,r2 /* r2 = 0 - r0 */
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#ifdef HAVE_LCD_CHARCELLS
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/* optimized player version, also works for recorders */
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.align 2
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.multi_transfer:
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mov.b @r4+,r1 /* load data byte from memory */
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.single_transfer:
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shll16 r1 /* shift data to most significant byte */
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shll8 r1
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shll r1 /* shift the msb into carry */
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neg r2,r0 /* copy negated precalculated port value */
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/* uses neg here for compatibility with recorder version */
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bt 1f /* data bit = 1? */
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and #(~LCD_SD),r0 /* no: r0 &= ~LCD_SD */
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1:
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shll r1 /* next shift here for alignment */
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mov.b r0,@r3 /* set data to port */
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or #(LCD_SC),r0 /* rise SC (independent of SD level) */
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mov.b r0,@r3 /* set to port */
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neg r2,r0
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bt 1f
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and #(~LCD_SD),r0
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1:
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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shll r1
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neg r2,r0
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bt 1f
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and #(~LCD_SD),r0
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1:
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shll r1
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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neg r2,r0
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bt 1f
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and #(~LCD_SD),r0
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1:
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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shll r1
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neg r2,r0
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bt 1f
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and #(~LCD_SD),r0
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1:
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shll r1
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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neg r2,r0
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bt 1f
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and #(~LCD_SD),r0
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1:
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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shll r1
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neg r2,r0
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bt 1f
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and #(~LCD_SD),r0
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1:
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shll r1
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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neg r2,r0
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bt 1f
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and #(~LCD_SD),r0
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1:
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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#else /* HAVE_LCD_CHARCELLS */
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/* further optimized version, exploits that SD is on bit 0 for recorders */
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.align 2
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.multi_transfer:
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mov.b @r4+,r1 /* load data byte from memory */
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nop
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.single_transfer:
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shll16 r1 /* shift data to most significant byte */
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shll8 r1
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not r1,r1 /* and invert for use with negc */
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shll r1 /* shift the MSB into carry */
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negc r2,r0 /* carry to SD, SC low */
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shll r1 /* next shift here for alignment */
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mov.b r0,@r3 /* set data to port */
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or #(LCD_SC),r0 /* rise SC (independent of SD level) */
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mov.b r0,@r3 /* set to port */
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negc r2,r0
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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shll r1
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negc r2,r0
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shll r1
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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negc r2,r0
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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shll r1
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negc r2,r0
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shll r1
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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negc r2,r0
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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shll r1
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negc r2,r0
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shll r1
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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negc r2,r0
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mov.b r0,@r3
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or #(LCD_SC),r0
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mov.b r0,@r3
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#endif /* HAVE_LCD_CHARCELLS */
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add #-1,r5 /* decrease byte count */
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tst r5,r5 /* r5 == 0 ? */
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bf .multi_transfer /* no: next iteration */
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or #(LCD_CS|LCD_DS|LCD_SD|LCD_SC),r0 /* restore port */
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rts
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mov.b r0,@r3
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/* This is the place to reenable the interrupts, if we have disabled
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* them. See above. */
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.align 2
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.lcdr:
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.long LCDR
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.end:
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.size _lcd_write_command,.end-_lcd_write_command
|
2004-10-26 06:53:34 +00:00
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#elif CONFIG_CPU == MCF5249
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.section .icode,"ax",@progbits
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.align 2
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.global lcd_write_command
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.type lcd_write_command,@function
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lcd_write_command:
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move.l (4,%sp),%d0
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lea MBAR2,%a1
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move.l #~8,%d1
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and.l %d1,(0xb4,%a1)
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move.w %d0,0xf0000000
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rts
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.align 2
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|
.global lcd_write_command_ex
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|
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.type lcd_write_command_ex,@function
|
2004-05-10 11:38:24 +00:00
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|
2004-10-26 06:53:34 +00:00
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lcd_write_command_ex:
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lea MBAR2,%a1
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move.l (4,%sp),%d0 /* Command */
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move.l #~8,%d1 /* Set A0 = 0 */
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and.l %d1,(0xb4,%a1)
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move.w %d0,0xf0000000 /* Write to LCD */
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not.l %d1 /* Set A0 = 1 */
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or.l %d1,(0xb4,%a1)
|
2005-01-27 00:00:05 +00:00
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move.l (8,%sp),%d0 /* Data */
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|
cmp.l #0xffffffff,%d0 /* -1? */
|
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|
|
beq.b .last
|
2004-10-26 06:53:34 +00:00
|
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|
move.w %d0,0xf0000000 /* Write to LCD */
|
2005-01-27 00:00:05 +00:00
|
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|
move.l (12,%sp),%d0 /* Data */
|
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|
cmp.l #0xffffffff,%d0 /* -1? */
|
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|
|
|
|
beq.b .last
|
|
|
|
|
|
move.w %d0,0xf0000000 /* Write to LCD */
|
|
|
|
|
|
|
|
|
|
|
|
.last:
|
2004-10-26 06:53:34 +00:00
|
|
|
|
rts
|
|
|
|
|
|
|
|
|
|
|
|
.align 2
|
|
|
|
|
|
.global lcd_write_data
|
|
|
|
|
|
.type lcd_write_data,@function
|
|
|
|
|
|
|
|
|
|
|
|
lcd_write_data:
|
|
|
|
|
|
move.l (4,%sp),%a0 /* Data pointer */
|
|
|
|
|
|
move.l (8,%sp),%d0 /* Length */
|
|
|
|
|
|
lea MBAR2,%a1
|
|
|
|
|
|
moveq #8,%d1
|
|
|
|
|
|
or.l %d1,(0xb4,%a1)
|
2005-02-10 22:29:19 +00:00
|
|
|
|
|
|
|
|
|
|
lea 0xf0000000,%a1
|
2004-10-26 06:53:34 +00:00
|
|
|
|
.loop:
|
|
|
|
|
|
move.b (%a0)+,%d1
|
2005-02-10 22:29:19 +00:00
|
|
|
|
move.w %d1,(%a1)
|
2004-10-26 06:53:34 +00:00
|
|
|
|
subq.l #1,%d0
|
|
|
|
|
|
bne .loop
|
|
|
|
|
|
rts
|
|
|
|
|
|
#endif
|
