197 lines
8 KiB
C
197 lines
8 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.7
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* XML versions: stmp3700:3.2.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3700__EMI__H__
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#define __HEADERGEN__STMP3700__EMI__H__
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#define REGS_EMI_BASE (0x80020000)
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#define REGS_EMI_VERSION "3.2.0"
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/**
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* Register: HW_EMI_CTRL
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* Address: 0
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* SCT: yes
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*/
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#define HW_EMI_CTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0))
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#define HW_EMI_CTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4))
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#define HW_EMI_CTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8))
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#define HW_EMI_CTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc))
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#define BP_EMI_CTRL_SFTRST 31
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#define BM_EMI_CTRL_SFTRST 0x80000000
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#define BF_EMI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BP_EMI_CTRL_CLKGATE 30
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#define BM_EMI_CTRL_CLKGATE 0x40000000
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#define BF_EMI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BP_EMI_CTRL_MEM_WIDTH 6
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#define BM_EMI_CTRL_MEM_WIDTH 0x40
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#define BF_EMI_CTRL_MEM_WIDTH(v) (((v) << 6) & 0x40)
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#define BP_EMI_CTRL_WRITE_PROTECT 5
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#define BM_EMI_CTRL_WRITE_PROTECT 0x20
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#define BF_EMI_CTRL_WRITE_PROTECT(v) (((v) << 5) & 0x20)
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#define BP_EMI_CTRL_RESET_OUT 4
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#define BM_EMI_CTRL_RESET_OUT 0x10
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#define BF_EMI_CTRL_RESET_OUT(v) (((v) << 4) & 0x10)
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#define BP_EMI_CTRL_CE_SELECT 0
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#define BM_EMI_CTRL_CE_SELECT 0xf
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#define BV_EMI_CTRL_CE_SELECT__NONE 0x0
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#define BV_EMI_CTRL_CE_SELECT__CE0 0x1
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#define BV_EMI_CTRL_CE_SELECT__CE1 0x2
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#define BV_EMI_CTRL_CE_SELECT__CE2 0x4
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#define BV_EMI_CTRL_CE_SELECT__CE3 0x8
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#define BF_EMI_CTRL_CE_SELECT(v) (((v) << 0) & 0xf)
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#define BF_EMI_CTRL_CE_SELECT_V(v) ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf)
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/**
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* Register: HW_EMI_STAT
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* Address: 0x10
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* SCT: no
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*/
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#define HW_EMI_STAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10))
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#define BP_EMI_STAT_DRAM_PRESENT 31
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#define BM_EMI_STAT_DRAM_PRESENT 0x80000000
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#define BF_EMI_STAT_DRAM_PRESENT(v) (((v) << 31) & 0x80000000)
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#define BP_EMI_STAT_NOR_PRESENT 30
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#define BM_EMI_STAT_NOR_PRESENT 0x40000000
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#define BF_EMI_STAT_NOR_PRESENT(v) (((v) << 30) & 0x40000000)
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#define BP_EMI_STAT_LARGE_DRAM_ENABLED 29
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#define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000
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#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) << 29) & 0x20000000)
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#define BP_EMI_STAT_DRAM_HALTED 1
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#define BM_EMI_STAT_DRAM_HALTED 0x2
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#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
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#define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1
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#define BF_EMI_STAT_DRAM_HALTED(v) (((v) << 1) & 0x2)
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#define BF_EMI_STAT_DRAM_HALTED_V(v) ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2)
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#define BP_EMI_STAT_NOR_BUSY 0
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#define BM_EMI_STAT_NOR_BUSY 0x1
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#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0
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#define BV_EMI_STAT_NOR_BUSY__BUSY 0x1
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#define BF_EMI_STAT_NOR_BUSY(v) (((v) << 0) & 0x1)
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#define BF_EMI_STAT_NOR_BUSY_V(v) ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1)
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/**
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* Register: HW_EMI_TIME
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* Address: 0x20
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* SCT: yes
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*/
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#define HW_EMI_TIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0))
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#define HW_EMI_TIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4))
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#define HW_EMI_TIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8))
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#define HW_EMI_TIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc))
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#define BP_EMI_TIME_THZ 24
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#define BM_EMI_TIME_THZ 0xf000000
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#define BF_EMI_TIME_THZ(v) (((v) << 24) & 0xf000000)
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#define BP_EMI_TIME_TDH 16
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#define BM_EMI_TIME_TDH 0xf0000
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#define BF_EMI_TIME_TDH(v) (((v) << 16) & 0xf0000)
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#define BP_EMI_TIME_TDS 8
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#define BM_EMI_TIME_TDS 0x1f00
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#define BF_EMI_TIME_TDS(v) (((v) << 8) & 0x1f00)
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#define BP_EMI_TIME_TAS 0
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#define BM_EMI_TIME_TAS 0xf
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#define BF_EMI_TIME_TAS(v) (((v) << 0) & 0xf)
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/**
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* Register: HW_EMI_DDR_TEST_MODE_CSR
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* Address: 0x30
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* SCT: yes
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*/
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#define HW_EMI_DDR_TEST_MODE_CSR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0))
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#define HW_EMI_DDR_TEST_MODE_CSR_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4))
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#define HW_EMI_DDR_TEST_MODE_CSR_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8))
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#define HW_EMI_DDR_TEST_MODE_CSR_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc))
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#define BP_EMI_DDR_TEST_MODE_CSR_DONE 1
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#define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x2
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#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v) (((v) << 1) & 0x2)
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#define BP_EMI_DDR_TEST_MODE_CSR_START 0
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#define BM_EMI_DDR_TEST_MODE_CSR_START 0x1
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#define BF_EMI_DDR_TEST_MODE_CSR_START(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_EMI_DEBUG
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* Address: 0x80
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* SCT: no
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*/
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#define HW_EMI_DEBUG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80))
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#define BP_EMI_DEBUG_NOR_STATE 0
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#define BM_EMI_DEBUG_NOR_STATE 0xf
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#define BF_EMI_DEBUG_NOR_STATE(v) (((v) << 0) & 0xf)
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/**
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* Register: HW_EMI_DDR_TEST_MODE_STATUS0
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* Address: 0x90
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* SCT: no
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*/
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#define HW_EMI_DDR_TEST_MODE_STATUS0 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90))
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#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0
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#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x1fff
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#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) (((v) << 0) & 0x1fff)
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/**
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* Register: HW_EMI_DDR_TEST_MODE_STATUS1
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* Address: 0xa0
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* SCT: no
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*/
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#define HW_EMI_DDR_TEST_MODE_STATUS1 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0))
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#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0
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#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x1fff
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#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) (((v) << 0) & 0x1fff)
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/**
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* Register: HW_EMI_DDR_TEST_MODE_STATUS2
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* Address: 0xb0
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* SCT: no
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*/
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#define HW_EMI_DDR_TEST_MODE_STATUS2 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0))
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#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0
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#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xffffffff
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#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_EMI_DDR_TEST_MODE_STATUS3
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* Address: 0xc0
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* SCT: no
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*/
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#define HW_EMI_DDR_TEST_MODE_STATUS3 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0))
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#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0
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#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xffffffff
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#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_EMI_VERSION
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* Address: 0xf0
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* SCT: no
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*/
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#define HW_EMI_VERSION (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0))
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#define BP_EMI_VERSION_MAJOR 24
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#define BM_EMI_VERSION_MAJOR 0xff000000
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#define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
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#define BP_EMI_VERSION_MINOR 16
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#define BM_EMI_VERSION_MINOR 0xff0000
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#define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
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#define BP_EMI_VERSION_STEP 0
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#define BM_EMI_VERSION_STEP 0xffff
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#define BF_EMI_VERSION_STEP(v) (((v) << 0) & 0xffff)
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#endif /* __HEADERGEN__STMP3700__EMI__H__ */
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