113 lines
4.8 KiB
C
113 lines
4.8 KiB
C
|
/***************************************************************************
|
||
|
|
* __________ __ ___.
|
||
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||
|
|
* \/ \/ \/ \/ \/
|
||
|
|
* This file was automatically generated by headergen, DO NOT EDIT it.
|
||
|
|
* headergen version: 3.0.0
|
||
|
|
* x1000 version: 1.0
|
||
|
|
* x1000 authors: Aidan MacDonald
|
||
|
|
*
|
||
|
|
* Copyright (C) 2015 by the authors
|
||
|
|
*
|
||
|
|
* This program is free software; you can redistribute it and/or
|
||
|
|
* modify it under the terms of the GNU General Public License
|
||
|
|
* as published by the Free Software Foundation; either version 2
|
||
|
|
* of the License, or (at your option) any later version.
|
||
|
|
*
|
||
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||
|
|
* KIND, either express or implied.
|
||
|
|
*
|
||
|
|
****************************************************************************/
|
||
|
|
#ifndef __HEADERGEN_DMA_H__
|
||
|
|
#define __HEADERGEN_DMA_H__
|
||
|
|
|
||
|
|
#include "macro.h"
|
||
|
|
|
||
|
|
#define REG_DMA_CTRL jz_reg(DMA_CTRL)
|
||
|
|
#define JA_DMA_CTRL (0xb3421000 + 0x0)
|
||
|
|
#define JT_DMA_CTRL JIO_32_RW
|
||
|
|
#define JN_DMA_CTRL DMA_CTRL
|
||
|
|
#define JI_DMA_CTRL
|
||
|
|
#define BP_DMA_CTRL_FMSC 31
|
||
|
|
#define BM_DMA_CTRL_FMSC 0x80000000
|
||
|
|
#define BF_DMA_CTRL_FMSC(v) (((v) & 0x1) << 31)
|
||
|
|
#define BFM_DMA_CTRL_FMSC(v) BM_DMA_CTRL_FMSC
|
||
|
|
#define BF_DMA_CTRL_FMSC_V(e) BF_DMA_CTRL_FMSC(BV_DMA_CTRL_FMSC__##e)
|
||
|
|
#define BFM_DMA_CTRL_FMSC_V(v) BM_DMA_CTRL_FMSC
|
||
|
|
#define BP_DMA_CTRL_FSSI 30
|
||
|
|
#define BM_DMA_CTRL_FSSI 0x40000000
|
||
|
|
#define BF_DMA_CTRL_FSSI(v) (((v) & 0x1) << 30)
|
||
|
|
#define BFM_DMA_CTRL_FSSI(v) BM_DMA_CTRL_FSSI
|
||
|
|
#define BF_DMA_CTRL_FSSI_V(e) BF_DMA_CTRL_FSSI(BV_DMA_CTRL_FSSI__##e)
|
||
|
|
#define BFM_DMA_CTRL_FSSI_V(v) BM_DMA_CTRL_FSSI
|
||
|
|
#define BP_DMA_CTRL_FTSSI 29
|
||
|
|
#define BM_DMA_CTRL_FTSSI 0x20000000
|
||
|
|
#define BF_DMA_CTRL_FTSSI(v) (((v) & 0x1) << 29)
|
||
|
|
#define BFM_DMA_CTRL_FTSSI(v) BM_DMA_CTRL_FTSSI
|
||
|
|
#define BF_DMA_CTRL_FTSSI_V(e) BF_DMA_CTRL_FTSSI(BV_DMA_CTRL_FTSSI__##e)
|
||
|
|
#define BFM_DMA_CTRL_FTSSI_V(v) BM_DMA_CTRL_FTSSI
|
||
|
|
#define BP_DMA_CTRL_FUART 28
|
||
|
|
#define BM_DMA_CTRL_FUART 0x10000000
|
||
|
|
#define BF_DMA_CTRL_FUART(v) (((v) & 0x1) << 28)
|
||
|
|
#define BFM_DMA_CTRL_FUART(v) BM_DMA_CTRL_FUART
|
||
|
|
#define BF_DMA_CTRL_FUART_V(e) BF_DMA_CTRL_FUART(BV_DMA_CTRL_FUART__##e)
|
||
|
|
#define BFM_DMA_CTRL_FUART_V(v) BM_DMA_CTRL_FUART
|
||
|
|
#define BP_DMA_CTRL_FAIC 27
|
||
|
|
#define BM_DMA_CTRL_FAIC 0x8000000
|
||
|
|
#define BF_DMA_CTRL_FAIC(v) (((v) & 0x1) << 27)
|
||
|
|
#define BFM_DMA_CTRL_FAIC(v) BM_DMA_CTRL_FAIC
|
||
|
|
#define BF_DMA_CTRL_FAIC_V(e) BF_DMA_CTRL_FAIC(BV_DMA_CTRL_FAIC__##e)
|
||
|
|
#define BFM_DMA_CTRL_FAIC_V(v) BM_DMA_CTRL_FAIC
|
||
|
|
#define BP_DMA_CTRL_HALT 3
|
||
|
|
#define BM_DMA_CTRL_HALT 0x8
|
||
|
|
#define BF_DMA_CTRL_HALT(v) (((v) & 0x1) << 3)
|
||
|
|
#define BFM_DMA_CTRL_HALT(v) BM_DMA_CTRL_HALT
|
||
|
|
#define BF_DMA_CTRL_HALT_V(e) BF_DMA_CTRL_HALT(BV_DMA_CTRL_HALT__##e)
|
||
|
|
#define BFM_DMA_CTRL_HALT_V(v) BM_DMA_CTRL_HALT
|
||
|
|
#define BP_DMA_CTRL_AR 2
|
||
|
|
#define BM_DMA_CTRL_AR 0x4
|
||
|
|
#define BF_DMA_CTRL_AR(v) (((v) & 0x1) << 2)
|
||
|
|
#define BFM_DMA_CTRL_AR(v) BM_DMA_CTRL_AR
|
||
|
|
#define BF_DMA_CTRL_AR_V(e) BF_DMA_CTRL_AR(BV_DMA_CTRL_AR__##e)
|
||
|
|
#define BFM_DMA_CTRL_AR_V(v) BM_DMA_CTRL_AR
|
||
|
|
#define BP_DMA_CTRL_ENABLE 0
|
||
|
|
#define BM_DMA_CTRL_ENABLE 0x1
|
||
|
|
#define BF_DMA_CTRL_ENABLE(v) (((v) & 0x1) << 0)
|
||
|
|
#define BFM_DMA_CTRL_ENABLE(v) BM_DMA_CTRL_ENABLE
|
||
|
|
#define BF_DMA_CTRL_ENABLE_V(e) BF_DMA_CTRL_ENABLE(BV_DMA_CTRL_ENABLE__##e)
|
||
|
|
#define BFM_DMA_CTRL_ENABLE_V(v) BM_DMA_CTRL_ENABLE
|
||
|
|
|
||
|
|
#define REG_DMA_IRQP jz_reg(DMA_IRQP)
|
||
|
|
#define JA_DMA_IRQP (0xb3421000 + 0x4)
|
||
|
|
#define JT_DMA_IRQP JIO_32_RW
|
||
|
|
#define JN_DMA_IRQP DMA_IRQP
|
||
|
|
#define JI_DMA_IRQP
|
||
|
|
|
||
|
|
#define REG_DMA_DB jz_reg(DMA_DB)
|
||
|
|
#define JA_DMA_DB (0xb3421000 + 0x8)
|
||
|
|
#define JT_DMA_DB JIO_32_RW
|
||
|
|
#define JN_DMA_DB DMA_DB
|
||
|
|
#define JI_DMA_DB
|
||
|
|
#define REG_DMA_DB_SET jz_reg(DMA_DB_SET)
|
||
|
|
#define JA_DMA_DB_SET (JA_DMA_DB + 0x4)
|
||
|
|
#define JT_DMA_DB_SET JIO_32_WO
|
||
|
|
#define JN_DMA_DB_SET DMA_DB
|
||
|
|
#define JI_DMA_DB_SET
|
||
|
|
|
||
|
|
#define REG_DMA_DIP jz_reg(DMA_DIP)
|
||
|
|
#define JA_DMA_DIP (0xb3421000 + 0x10)
|
||
|
|
#define JT_DMA_DIP JIO_32_RW
|
||
|
|
#define JN_DMA_DIP DMA_DIP
|
||
|
|
#define JI_DMA_DIP
|
||
|
|
|
||
|
|
#define REG_DMA_DIC jz_reg(DMA_DIC)
|
||
|
|
#define JA_DMA_DIC (0xb3421000 + 0x14)
|
||
|
|
#define JT_DMA_DIC JIO_32_RW
|
||
|
|
#define JN_DMA_DIC DMA_DIC
|
||
|
|
#define JI_DMA_DIC
|
||
|
|
|
||
|
|
#endif /* __HEADERGEN_DMA_H__*/
|