2007-10-18 22:37:33 +00:00
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/*
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libdemac - A Monkey's Audio decoder
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$Id$
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Copyright (C) Dave Chapman 2007
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Coldfire vector math copyright (C) 2007 Jens Arnold
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
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*/
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2010-02-02 22:50:21 +00:00
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#define FUSED_VECTOR_MATH
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#define PREPARE_SCALARPRODUCT coldfire_set_macsr(0); /* signed integer mode */
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2010-03-03 20:52:02 +00:00
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#define REPEAT_2(x) x x
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#define REPEAT_3(x) x x x
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#define REPEAT_7(x) x x x x x x x
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2010-02-02 22:50:21 +00:00
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/* Calculate scalarproduct, then add a 2nd vector (fused for performance)
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* This version fetches data as 32 bit words, and *recommends* v1 to be
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* 32 bit aligned. It also assumes that f2 and s2 are either both 32 bit
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* aligned or both unaligned. Performance will suffer if either condition
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* isn't met. It also needs EMAC in signed integer mode. */
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static inline int32_t vector_sp_add(int16_t* v1, int16_t* f2, int16_t* s2)
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2007-10-18 22:37:33 +00:00
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{
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2010-02-02 22:50:21 +00:00
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int res;
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2007-10-25 18:58:16 +00:00
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#if ORDER > 16
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int cnt = ORDER>>4;
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#endif
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2010-02-02 22:50:21 +00:00
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#define ADDHALFREGS(s1, s2, sum) /* Add register halves straight. */ \
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"move.l " #s1 ", " #sum "\n" /* 's1' and 's2' can be A or D */ \
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"add.l " #s2 ", " #s1 "\n" /* regs, 'sum' must be a D reg. */ \
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"clr.w " #sum " \n" /* 's1' is clobbered! */ \
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"add.l " #s2 ", " #sum "\n" \
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2007-10-25 18:58:16 +00:00
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"move.w " #s1 ", " #sum "\n"
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#define ADDHALFXREGS(s1, s2, sum) /* Add register halves across. */ \
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"clr.w " #sum " \n" /* Needs 'sum' pre-swapped, swaps */ \
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"add.l " #s1 ", " #sum "\n" /* 's2', and clobbers 's1'. */ \
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"swap " #s2 " \n" /* 's1' can be an A or D reg. */ \
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"add.l " #s2 ", " #s1 "\n" /* 'sum' and 's2' must be D regs. */ \
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2007-10-18 22:37:33 +00:00
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"move.w " #s1 ", " #sum "\n"
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asm volatile (
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2010-02-02 22:50:21 +00:00
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"move.l %[f2], %%d0 \n"
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"and.l #2, %%d0 \n"
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"jeq 20f \n"
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"10: \n"
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"move.w (%[f2])+, %%d0 \n"
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"move.w (%[s2])+, %%d1 \n"
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"swap %%d1 \n"
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"1: \n"
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2010-03-03 20:52:02 +00:00
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REPEAT_2(
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2010-02-02 22:50:21 +00:00
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"movem.l (%[v1]), %%d6-%%d7/%%a0-%%a1 \n"
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"mac.w %%d0l, %%d6u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%d6l, (%[s2])+, %%d2, %%acc0\n"
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ADDHALFXREGS(%%d6, %%d2, %%d1)
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"mac.w %%d0l, %%d7u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%d7l, (%[s2])+, %%d6, %%acc0\n"
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"move.l %%d1, (%[v1])+ \n"
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ADDHALFXREGS(%%d7, %%d6, %%d2)
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"mac.w %%d0l, %%a0u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%a0l, (%[s2])+, %%d7, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFXREGS(%%a0, %%d7, %%d6)
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"mac.w %%d0l, %%a1u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%a1l, (%[s2])+, %%d1, %%acc0\n"
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"move.l %%d6, (%[v1])+ \n"
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ADDHALFXREGS(%%a1, %%d1, %%d7)
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"move.l %%d7, (%[v1])+ \n"
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2010-03-03 20:52:02 +00:00
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)
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2010-02-02 22:50:21 +00:00
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2007-10-25 18:58:16 +00:00
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#if ORDER > 16
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2010-02-02 22:50:21 +00:00
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"subq.l #1, %[res] \n"
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"bne.w 1b \n"
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#endif
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"jra 99f \n"
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2007-10-25 18:58:16 +00:00
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2010-02-02 22:50:21 +00:00
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"20: \n"
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"move.l (%[f2])+, %%d0 \n"
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"1: \n"
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"movem.l (%[v1]), %%d6-%%d7/%%a0-%%a1 \n"
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"mac.w %%d0u, %%d6u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%d6l, (%[f2])+, %%d0, %%acc0\n"
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ADDHALFREGS(%%d6, %%d1, %%d2)
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"mac.w %%d0u, %%d7u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%d7l, (%[f2])+, %%d0, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%d7, %%d1, %%d2)
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"mac.w %%d0u, %%a0u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%a0l, (%[f2])+, %%d0, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%a0, %%d1, %%d2)
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"mac.w %%d0u, %%a1u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%a1l, (%[f2])+, %%d0, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%a1, %%d1, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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"movem.l (%[v1]), %%d6-%%d7/%%a0-%%a1 \n"
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"mac.w %%d0u, %%d6u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%d6l, (%[f2])+, %%d0, %%acc0\n"
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ADDHALFREGS(%%d6, %%d1, %%d2)
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"mac.w %%d0u, %%d7u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%d7l, (%[f2])+, %%d0, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%d7, %%d1, %%d2)
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"mac.w %%d0u, %%a0u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%a0l, (%[f2])+, %%d0, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%a0, %%d1, %%d2)
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"mac.w %%d0u, %%a1u, (%[s2])+, %%d1, %%acc0\n"
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#if ORDER > 16
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"mac.w %%d0l, %%a1l, (%[f2])+, %%d0, %%acc0\n"
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#else
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"mac.w %%d0l, %%a1l, %%acc0 \n"
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2007-10-18 22:37:33 +00:00
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#endif
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2010-02-02 22:50:21 +00:00
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%a1, %%d1, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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2007-10-18 22:37:33 +00:00
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#if ORDER > 16
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2010-02-02 22:50:21 +00:00
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"subq.l #1, %[res] \n"
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"bne.w 1b \n"
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2007-10-18 22:37:33 +00:00
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#endif
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2010-02-02 22:50:21 +00:00
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"99: \n"
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"movclr.l %%acc0, %[res] \n"
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2007-10-18 22:37:33 +00:00
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: /* outputs */
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2010-02-02 22:50:21 +00:00
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[v1]"+a"(v1),
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[f2]"+a"(f2),
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[s2]"+a"(s2),
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[res]"=d"(res)
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: /* inputs */
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2007-10-25 18:58:16 +00:00
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#if ORDER > 16
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2010-02-02 22:50:21 +00:00
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[cnt]"[res]"(cnt)
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2007-10-25 18:58:16 +00:00
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#endif
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2007-10-18 22:37:33 +00:00
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: /* clobbers */
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2010-02-02 22:50:21 +00:00
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"d0", "d1", "d2", "d6", "d7",
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"a0", "a1", "memory"
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2007-10-18 22:37:33 +00:00
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);
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2010-02-02 22:50:21 +00:00
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return res;
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2007-10-18 22:37:33 +00:00
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}
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2010-02-02 22:50:21 +00:00
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/* Calculate scalarproduct, then subtract a 2nd vector (fused for performance)
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* This version fetches data as 32 bit words, and *recommends* v1 to be
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* 32 bit aligned. It also assumes that f2 and s2 are either both 32 bit
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* aligned or both unaligned. Performance will suffer if either condition
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* isn't met. It also needs EMAC in signed integer mode. */
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static inline int32_t vector_sp_sub(int16_t* v1, int16_t* f2, int16_t* s2)
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2007-10-18 22:37:33 +00:00
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{
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2010-02-02 22:50:21 +00:00
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int res;
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2007-10-25 18:58:16 +00:00
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#if ORDER > 16
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int cnt = ORDER>>4;
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#endif
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#define SUBHALFREGS(min, sub, dif) /* Subtract register halves straight. */ \
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"move.l " #min ", " #dif "\n" /* 'min' can be an A or D reg */ \
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"sub.l " #sub ", " #min "\n" /* 'sub' and 'dif' must be D regs */ \
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"clr.w " #sub "\n" /* 'min' and 'sub' are clobbered! */ \
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"sub.l " #sub ", " #dif "\n" \
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2007-10-18 22:37:33 +00:00
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"move.w " #min ", " #dif "\n"
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2007-10-25 18:58:16 +00:00
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#define SUBHALFXREGS(min, s2, s1d) /* Subtract register halves across. */ \
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"clr.w " #s1d "\n" /* Needs 's1d' pre-swapped, swaps */ \
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"sub.l " #s1d ", " #min "\n" /* 's2' and clobbers 'min'. */ \
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"move.l " #min ", " #s1d "\n" /* 'min' can be an A or D reg, */ \
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"swap " #s2 "\n" /* 's2' and 's1d' must be D regs. */ \
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"sub.l " #s2 ", " #min "\n" \
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"move.w " #min ", " #s1d "\n"
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2007-10-18 22:37:33 +00:00
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asm volatile (
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2010-02-02 22:50:21 +00:00
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"move.l %[f2], %%d0 \n"
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"and.l #2, %%d0 \n"
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"jeq 20f \n"
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"10: \n"
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"move.w (%[f2])+, %%d0 \n"
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"move.w (%[s2])+, %%d1 \n"
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"swap %%d1 \n"
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"1: \n"
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2010-03-03 20:52:02 +00:00
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REPEAT_2(
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2010-02-02 22:50:21 +00:00
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"movem.l (%[v1]), %%d6-%%d7/%%a0-%%a1 \n"
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"mac.w %%d0l, %%d6u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%d6l, (%[s2])+, %%d2, %%acc0\n"
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SUBHALFXREGS(%%d6, %%d2, %%d1)
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"mac.w %%d0l, %%d7u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%d7l, (%[s2])+, %%d6, %%acc0\n"
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"move.l %%d1, (%[v1])+ \n"
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SUBHALFXREGS(%%d7, %%d6, %%d2)
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"mac.w %%d0l, %%a0u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%a0l, (%[s2])+, %%d7, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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SUBHALFXREGS(%%a0, %%d7, %%d6)
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"mac.w %%d0l, %%a1u, (%[f2])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%a1l, (%[s2])+, %%d1, %%acc0\n"
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"move.l %%d6, (%[v1])+ \n"
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SUBHALFXREGS(%%a1, %%d1, %%d7)
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"move.l %%d7, (%[v1])+ \n"
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2010-03-03 20:52:02 +00:00
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)
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2010-02-02 22:50:21 +00:00
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2007-10-25 18:58:16 +00:00
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#if ORDER > 16
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2010-02-02 22:50:21 +00:00
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"subq.l #1, %[res] \n"
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"bne.w 1b \n"
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2007-10-18 22:37:33 +00:00
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#endif
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2007-10-19 07:30:55 +00:00
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2010-02-02 22:50:21 +00:00
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"jra 99f \n"
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"20: \n"
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"move.l (%[f2])+, %%d0 \n"
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"1: \n"
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"movem.l (%[v1]), %%d6-%%d7/%%a0-%%a1 \n"
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"mac.w %%d0u, %%d6u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%d6l, (%[f2])+, %%d0, %%acc0\n"
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SUBHALFREGS(%%d6, %%d1, %%d2)
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"mac.w %%d0u, %%d7u, (%[s2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%d7l, (%[f2])+, %%d0, %%acc0\n"
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"move.l %%d2, (%[v1])+ \n"
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SUBHALFREGS(%%d7, %%d1, %%d2)
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"mac.w %%d0u, %%a0u, (%[s2])+, %%d1, %%acc0\n"
|
|
|
|
|
"mac.w %%d0l, %%a0l, (%[f2])+, %%d0, %%acc0\n"
|
|
|
|
|
"move.l %%d2, (%[v1])+ \n"
|
|
|
|
|
SUBHALFREGS(%%a0, %%d1, %%d2)
|
|
|
|
|
"mac.w %%d0u, %%a1u, (%[s2])+, %%d1, %%acc0\n"
|
|
|
|
|
"mac.w %%d0l, %%a1l, (%[f2])+, %%d0, %%acc0\n"
|
|
|
|
|
"move.l %%d2, (%[v1])+ \n"
|
|
|
|
|
SUBHALFREGS(%%a1, %%d1, %%d2)
|
|
|
|
|
"move.l %%d2, (%[v1])+ \n"
|
|
|
|
|
|
|
|
|
|
"movem.l (%[v1]), %%d6-%%d7/%%a0-%%a1 \n"
|
|
|
|
|
"mac.w %%d0u, %%d6u, (%[s2])+, %%d1, %%acc0\n"
|
|
|
|
|
"mac.w %%d0l, %%d6l, (%[f2])+, %%d0, %%acc0\n"
|
|
|
|
|
SUBHALFREGS(%%d6, %%d1, %%d2)
|
|
|
|
|
"mac.w %%d0u, %%d7u, (%[s2])+, %%d1, %%acc0\n"
|
|
|
|
|
"mac.w %%d0l, %%d7l, (%[f2])+, %%d0, %%acc0\n"
|
|
|
|
|
"move.l %%d2, (%[v1])+ \n"
|
|
|
|
|
SUBHALFREGS(%%d7, %%d1, %%d2)
|
|
|
|
|
"mac.w %%d0u, %%a0u, (%[s2])+, %%d1, %%acc0\n"
|
|
|
|
|
"mac.w %%d0l, %%a0l, (%[f2])+, %%d0, %%acc0\n"
|
|
|
|
|
"move.l %%d2, (%[v1])+ \n"
|
|
|
|
|
SUBHALFREGS(%%a0, %%d1, %%d2)
|
|
|
|
|
"mac.w %%d0u, %%a1u, (%[s2])+, %%d1, %%acc0\n"
|
|
|
|
|
#if ORDER > 16
|
|
|
|
|
"mac.w %%d0l, %%a1l, (%[f2])+, %%d0, %%acc0\n"
|
|
|
|
|
#else
|
|
|
|
|
"mac.w %%d0l, %%a1l, %%acc0 \n"
|
|
|
|
|
#endif
|
|
|
|
|
"move.l %%d2, (%[v1])+ \n"
|
|
|
|
|
SUBHALFREGS(%%a1, %%d1, %%d2)
|
|
|
|
|
"move.l %%d2, (%[v1])+ \n"
|
|
|
|
|
#if ORDER > 16
|
|
|
|
|
"subq.l #1, %[res] \n"
|
|
|
|
|
"bne.w 1b \n"
|
2007-10-18 22:37:33 +00:00
|
|
|
#endif
|
2007-10-25 18:58:16 +00:00
|
|
|
|
2010-02-02 22:50:21 +00:00
|
|
|
"99: \n"
|
|
|
|
|
"movclr.l %%acc0, %[res] \n"
|
2007-10-18 22:37:33 +00:00
|
|
|
: /* outputs */
|
2010-02-02 22:50:21 +00:00
|
|
|
[v1]"+a"(v1),
|
|
|
|
|
[f2]"+a"(f2),
|
|
|
|
|
[s2]"+a"(s2),
|
|
|
|
|
[res]"=d"(res)
|
|
|
|
|
: /* inputs */
|
2007-10-25 18:58:16 +00:00
|
|
|
#if ORDER > 16
|
2010-02-02 22:50:21 +00:00
|
|
|
[cnt]"[res]"(cnt)
|
2007-10-25 18:58:16 +00:00
|
|
|
#endif
|
2007-10-18 22:37:33 +00:00
|
|
|
: /* clobbers */
|
2010-02-02 22:50:21 +00:00
|
|
|
"d0", "d1", "d2", "d6", "d7",
|
|
|
|
|
"a0", "a1", "memory"
|
|
|
|
|
|
2007-10-18 22:37:33 +00:00
|
|
|
);
|
2010-02-02 22:50:21 +00:00
|
|
|
return res;
|
2007-10-18 22:37:33 +00:00
|
|
|
}
|
|
|
|
|
|
2007-10-25 18:58:16 +00:00
|
|
|
/* This version fetches data as 32 bit words, and *recommends* v1 to be
|
|
|
|
|
* 32 bit aligned, otherwise performance will suffer. It also needs EMAC
|
2010-02-02 22:50:21 +00:00
|
|
|
* in signed integer mode. */
|
2007-10-18 22:37:33 +00:00
|
|
|
static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
|
|
|
|
|
{
|
2008-11-19 21:31:33 +00:00
|
|
|
int res;
|
|
|
|
|
#if ORDER > 16
|
2010-02-02 22:50:21 +00:00
|
|
|
int cnt = ORDER>>4;
|
2008-11-19 21:31:33 +00:00
|
|
|
#endif
|
2007-10-18 22:37:33 +00:00
|
|
|
|
|
|
|
|
asm volatile (
|
2007-10-25 18:58:16 +00:00
|
|
|
"move.l %[v2], %%d0 \n"
|
|
|
|
|
"and.l #2, %%d0 \n"
|
|
|
|
|
"jeq 20f \n"
|
|
|
|
|
|
|
|
|
|
"10: \n"
|
|
|
|
|
"move.l (%[v1])+, %%d0 \n"
|
|
|
|
|
"move.w (%[v2])+, %%d1 \n"
|
|
|
|
|
"1: \n"
|
2010-03-03 20:52:02 +00:00
|
|
|
REPEAT_7(
|
2008-11-19 21:31:33 +00:00
|
|
|
"mac.w %%d0u, %%d1l, (%[v2])+, %%d1, %%acc0\n"
|
|
|
|
|
"mac.w %%d0l, %%d1u, (%[v1])+, %%d0, %%acc0\n"
|
2010-03-03 20:52:02 +00:00
|
|
|
)
|
2008-11-19 21:31:33 +00:00
|
|
|
|
2007-10-25 18:58:16 +00:00
|
|
|
"mac.w %%d0u, %%d1l, (%[v2])+, %%d1, %%acc0\n"
|
2010-02-02 22:50:21 +00:00
|
|
|
#if ORDER > 16
|
2007-10-25 18:58:16 +00:00
|
|
|
"mac.w %%d0l, %%d1u, (%[v1])+, %%d0, %%acc0\n"
|
|
|
|
|
"subq.l #1, %[res] \n"
|
2010-02-02 22:50:21 +00:00
|
|
|
"bne.b 1b \n"
|
2007-10-25 18:58:16 +00:00
|
|
|
#else
|
|
|
|
|
"mac.w %%d0l, %%d1u, %%acc0 \n"
|
2007-10-18 22:37:33 +00:00
|
|
|
#endif
|
2007-10-25 18:58:16 +00:00
|
|
|
"jra 99f \n"
|
|
|
|
|
|
|
|
|
|
"20: \n"
|
2007-10-18 22:37:33 +00:00
|
|
|
"move.l (%[v1])+, %%d0 \n"
|
|
|
|
|
"move.l (%[v2])+, %%d1 \n"
|
|
|
|
|
"1: \n"
|
2010-03-03 20:52:02 +00:00
|
|
|
REPEAT_3(
|
2008-11-19 21:31:33 +00:00
|
|
|
"mac.w %%d0u, %%d1u, (%[v1])+, %%d2, %%acc0\n"
|
|
|
|
|
"mac.w %%d0l, %%d1l, (%[v2])+, %%d1, %%acc0\n"
|
|
|
|
|
"mac.w %%d2u, %%d1u, (%[v1])+, %%d0, %%acc0\n"
|
|
|
|
|
"mac.w %%d2l, %%d1l, (%[v2])+, %%d1, %%acc0\n"
|
2010-03-03 20:52:02 +00:00
|
|
|
)
|
2008-11-19 21:31:33 +00:00
|
|
|
|
2007-10-18 22:37:33 +00:00
|
|
|
"mac.w %%d0u, %%d1u, (%[v1])+, %%d2, %%acc0\n"
|
2007-10-25 18:58:16 +00:00
|
|
|
"mac.w %%d0l, %%d1l, (%[v2])+, %%d1, %%acc0\n"
|
2010-02-02 22:50:21 +00:00
|
|
|
#if ORDER > 16
|
2007-10-25 18:58:16 +00:00
|
|
|
"mac.w %%d2u, %%d1u, (%[v1])+, %%d0, %%acc0\n"
|
|
|
|
|
"mac.w %%d2l, %%d1l, (%[v2])+, %%d1, %%acc0\n"
|
2007-10-18 22:37:33 +00:00
|
|
|
"subq.l #1, %[res] \n"
|
2010-02-02 22:50:21 +00:00
|
|
|
"bne.b 1b \n"
|
2007-10-18 22:37:33 +00:00
|
|
|
#else
|
2007-10-25 18:58:16 +00:00
|
|
|
"mac.w %%d2u, %%d1u, %%acc0 \n"
|
|
|
|
|
"mac.w %%d2l, %%d1l, %%acc0 \n"
|
2007-10-18 22:37:33 +00:00
|
|
|
#endif
|
2007-10-25 18:58:16 +00:00
|
|
|
|
|
|
|
|
"99: \n"
|
2007-10-18 22:37:33 +00:00
|
|
|
"movclr.l %%acc0, %[res] \n"
|
|
|
|
|
: /* outputs */
|
|
|
|
|
[v1]"+a"(v1),
|
|
|
|
|
[v2]"+a"(v2),
|
2007-10-25 18:58:16 +00:00
|
|
|
[res]"=d"(res)
|
2007-10-18 22:37:33 +00:00
|
|
|
: /* inputs */
|
2010-02-02 22:50:21 +00:00
|
|
|
#if ORDER > 16
|
2007-10-25 18:58:16 +00:00
|
|
|
[cnt]"[res]"(cnt)
|
|
|
|
|
#endif
|
2007-10-18 22:37:33 +00:00
|
|
|
: /* clobbers */
|
2007-10-25 18:58:16 +00:00
|
|
|
"d0", "d1", "d2"
|
2007-10-18 22:37:33 +00:00
|
|
|
);
|
|
|
|
|
return res;
|
|
|
|
|
}
|
