97 lines
4.1 KiB
C
97 lines
4.1 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Daniel Ankers
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Core locks using Peterson's mutual exclusion algorithm.
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* ASM optimized version of C code, see firmware/asm/corelock.c */
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#include "cpu.h"
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/*---------------------------------------------------------------------------
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* Wait for the corelock to become free and acquire it when it does.
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*---------------------------------------------------------------------------
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*/
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void __attribute__((naked)) corelock_lock(struct corelock *cl)
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{
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/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
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asm volatile (
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"mov r1, %0 \n" /* r1 = PROCESSOR_ID */
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"ldrb r1, [r1] \n"
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"strb r1, [r0, r1, lsr #7] \n" /* cl->myl[core] = core */
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"eor r2, r1, #0xff \n" /* r2 = othercore */
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"strb r2, [r0, #2] \n" /* cl->turn = othercore */
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"1: \n"
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"ldrb r3, [r0, r2, lsr #7] \n" /* cl->myl[othercore] == 0 ? */
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"cmp r3, #0 \n" /* yes? lock acquired */
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"bxeq lr \n"
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"ldrb r3, [r0, #2] \n" /* || cl->turn == core ? */
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"cmp r3, r1 \n"
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"bxeq lr \n" /* yes? lock acquired */
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"b 1b \n" /* keep trying */
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: : "i"(&PROCESSOR_ID)
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);
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(void)cl;
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}
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/*---------------------------------------------------------------------------
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* Try to aquire the corelock. If free, caller gets it, otherwise return 0.
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*---------------------------------------------------------------------------
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*/
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int __attribute__((naked)) corelock_try_lock(struct corelock *cl)
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{
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/* Relies on the fact that core IDs are complementary bitmasks (0x55,0xaa) */
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asm volatile (
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"mov r1, %0 \n" /* r1 = PROCESSOR_ID */
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"ldrb r1, [r1] \n"
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"mov r3, r0 \n"
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"strb r1, [r0, r1, lsr #7] \n" /* cl->myl[core] = core */
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"eor r2, r1, #0xff \n" /* r2 = othercore */
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"strb r2, [r0, #2] \n" /* cl->turn = othercore */
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"ldrb r0, [r3, r2, lsr #7] \n" /* cl->myl[othercore] == 0 ? */
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"eors r0, r0, r2 \n" /* yes? lock acquired */
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"bxne lr \n"
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"ldrb r0, [r3, #2] \n" /* || cl->turn == core? */
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"ands r0, r0, r1 \n"
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"streqb r0, [r3, r1, lsr #7] \n" /* if not, cl->myl[core] = 0 */
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"bx lr \n" /* return result */
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: : "i"(&PROCESSOR_ID)
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);
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return 0;
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(void)cl;
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}
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/*---------------------------------------------------------------------------
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* Release ownership of the corelock
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*---------------------------------------------------------------------------
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*/
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void __attribute__((naked)) corelock_unlock(struct corelock *cl)
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{
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asm volatile (
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"mov r1, %0 \n" /* r1 = PROCESSOR_ID */
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"ldrb r1, [r1] \n"
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"mov r2, #0 \n" /* cl->myl[core] = 0 */
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"strb r2, [r0, r1, lsr #7] \n"
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"bx lr \n"
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: : "i"(&PROCESSOR_ID)
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);
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(void)cl;
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}
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