2014-09-23 11:30:17 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2014 by Marcin Bukat
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Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "usb_drv.h"
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#include "config.h"
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#include "memory.h"
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#include "target.h"
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#include "atj213x.h"
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#define USB_FULL_SPEED 0
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#define USB_HIGH_SPEED 1
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volatile bool setup_data_valid = false;
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volatile int udc_speed = USB_FULL_SPEED;
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2016-02-29 07:26:33 +00:00
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struct endpoint_t
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{
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void *buf;
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int length;
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bool zlp;
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bool finished;
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};
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static volatile struct endpoint_t ep0in = {NULL,0,false,false};
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static volatile struct endpoint_t ep0out = {NULL,0,false,false};
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2014-09-23 11:30:17 +00:00
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static void usb_copy_from(void *ptr, volatile void *reg, size_t sz)
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{
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uint32_t *p = ptr;
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volatile uint32_t *rp = reg;
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/* do not overflow the destination buffer ! */
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while(sz >= 4)
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{
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*p++ = *rp++;
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sz -= 4;
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}
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if(sz == 0)
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return;
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/* reminder */
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uint32_t cache = *rp;
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uint8_t *p8 = (void *)p;
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while(sz-- > 0)
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{
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*p8++ = cache;
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cache >>= 8;
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}
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}
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static void usb_copy_to(volatile void *reg, void *ptr, size_t sz)
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{
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uint32_t *p = ptr;
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volatile uint32_t *rp = reg;
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sz = (sz + 3) / 4;
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/* read may overflow the source buffer but
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* it will not overwrite anything
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*/
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while(sz-- > 0)
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*rp++ = *p++;
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}
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void usb_drv_init(void)
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{
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OTG_USBCS |= 0x40; /* soft disconnect */
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OTG_ENDPRST = 0x10; /* reset all ep fifos */
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OTG_ENDPRST = 0x70;
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OTG_ENDPRST = 0x00;
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OTG_ENDPRST = 0x60;
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OTG_USBIRQ = 0xff; /* clear all pending interrupts */
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OTG_OTGIRQ = 0xff;
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OTG_IN04IRQ = 0xff;
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OTG_OUT04IRQ = 0xff;
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OTG_USBEIRQ = 0x50; /* UDC ? with 0x40 there is irq storm */
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OTG_USBIEN = (1<<5) | (1<<4) | (1<<0); /* HS, Reset, Setup_data */
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OTG_OTGIEN = 0;
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2016-02-29 07:26:33 +00:00
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/* enable interrupts from ep0 */
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OTG_IN04IEN = 1;
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OTG_OUT04IEN = 1;
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2014-09-23 11:30:17 +00:00
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/* unmask UDC interrupt in interrupt controller */
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INTC_MSK = (1<<4);
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target_mdelay(100);
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OTG_USBCS &= ~0x40; /* soft connect */
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}
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int usb_drv_recv_setup(struct usb_ctrlrequest *req)
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{
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while (!setup_data_valid)
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;
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usb_copy_from(req, &OTG_SETUPDAT, sizeof(struct usb_ctrlrequest));
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setup_data_valid = false;
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return 0;
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}
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int usb_drv_port_speed(void)
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{
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return (int)udc_speed;
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}
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/* Set the address (usually it's in a register).
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* There is a problem here: some controller want the address to be set between
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* control out and ack and some want to wait for the end of the transaction.
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* In the first case, you need to write some code special code when getting
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* setup packets and ignore this function (have a look at other drives)
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*/
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void usb_drv_set_address(int address)
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{
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(void)address;
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/* UDC sets this automaticaly */
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}
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2016-02-29 07:26:33 +00:00
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static void ep0_write(void)
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{
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int xfer_size = MIN(ep0in.length, 64);
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/* copy data to UDC buffer */
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usb_copy_to(&OTG_EP0INDAT, ep0in.buf, xfer_size);
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ep0in.buf += xfer_size;
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ep0in.length -= xfer_size;
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/* this marks data as ready to send */
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OTG_IN0BC = xfer_size;
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}
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2014-09-23 11:30:17 +00:00
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/* TODO: Maybe adapt to irq scheme */
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int usb_drv_send(int endpoint, void *ptr, int length)
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{
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(void)endpoint;
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2016-02-29 07:26:33 +00:00
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if (length)
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2014-09-23 11:30:17 +00:00
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{
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2016-02-29 07:26:33 +00:00
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ep0in.length = length;
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ep0in.buf = ptr;
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ep0in.zlp = (length % 64 == 0) ? true : false;
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ep0in.finished = false;
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2014-09-23 11:30:17 +00:00
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2016-02-29 07:26:33 +00:00
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ep0_write();
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2014-09-23 11:30:17 +00:00
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2016-02-29 07:26:33 +00:00
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while(!ep0in.finished)
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2014-09-23 11:30:17 +00:00
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;
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}
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2016-02-29 07:26:33 +00:00
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else
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{
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2014-09-23 11:30:17 +00:00
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OTG_EP0CS = 2;
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2016-02-29 07:26:33 +00:00
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}
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2014-09-23 11:30:17 +00:00
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return 0;
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}
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2016-02-29 07:26:33 +00:00
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static int ep0_read(void)
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{
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int xfer_size = OTG_OUT0BC;
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usb_copy_from(ep0out.buf, &OTG_EP0OUTDAT, xfer_size);
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ep0out.buf += xfer_size;
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ep0out.length -= xfer_size;
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return xfer_size;
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}
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2014-09-23 11:30:17 +00:00
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/* TODO: Maybe adapt to irq scheme */
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int usb_drv_recv(int endpoint, void* ptr, int length)
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{
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(void)endpoint;
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2016-02-29 07:26:33 +00:00
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ep0out.length = length;
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ep0out.buf = ptr;
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ep0out.zlp = (length == 0) ? true : false;
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ep0out.finished = false;
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2014-09-23 11:30:17 +00:00
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2016-02-29 07:26:33 +00:00
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/* Arm receiving buffer by writing
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* any value to OUT0BC. This sets
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* OUT_BUSY bit in EP0CS until the data
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* are correctly received and ACK'd
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*/
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OTG_OUT0BC = 0;
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2014-09-23 11:30:17 +00:00
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2016-02-29 07:26:33 +00:00
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while (!ep0out.finished)
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;
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2014-09-23 11:30:17 +00:00
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2016-02-29 07:26:33 +00:00
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return (length - ep0out.length);
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2014-09-23 11:30:17 +00:00
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}
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void usb_drv_stall(int endpoint, bool stall, bool in)
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{
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(void)endpoint;
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(void)in;
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/* only EP0 in hwstub */
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if (stall)
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OTG_EP0CS |= 1;
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else
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OTG_EP0CS &= ~1;
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}
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void usb_drv_exit(void)
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{
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}
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2016-02-29 07:26:33 +00:00
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void INT_UDC(void)
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{
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/* get possible sources */
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unsigned int usbirq = OTG_USBIRQ;
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unsigned int otgirq = OTG_OTGIRQ;
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unsigned int epinirq = OTG_IN04IRQ;
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unsigned int epoutirq = OTG_OUT04IRQ;
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/* HS, Reset, Setup */
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if (usbirq)
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{
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if (usbirq & (1<<5))
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{
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/* HS irq */
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udc_speed = USB_HIGH_SPEED;
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}
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else if (usbirq & (1<<4))
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{
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/* Reset */
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udc_speed = USB_FULL_SPEED;
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/* clear all pending irqs */
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OTG_OUT04IRQ = 0xff;
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OTG_IN04IRQ = 0xff;
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}
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else if (usbirq & (1<<0))
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{
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/* Setup data valid */
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setup_data_valid = true;
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}
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/* clear irq flags */
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OTG_USBIRQ = usbirq;
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}
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if (epoutirq)
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{
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if (ep0_read() == 64)
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{
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/* rearm receive buffer */
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OTG_OUT0BC = 0;
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}
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else
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{
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if (ep0out.length == 0 && ep0out.zlp)
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{
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OTG_EP0CS = 2;
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}
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ep0out.finished = true;
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}
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OTG_OUT04IRQ = epoutirq;
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}
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if (epinirq)
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{
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if (ep0in.length)
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{
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ep0_write();
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}
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else
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{
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if (ep0in.zlp)
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{
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OTG_EP0CS = 2;
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}
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ep0in.finished = true;
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}
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/* ack interrupt */
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OTG_IN04IRQ = epinirq;
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}
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if (otgirq)
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{
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OTG_OTGIRQ = otgirq;
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}
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OTG_USBEIRQ = 0x50;
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}
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