156 lines
5.2 KiB
C
156 lines
5.2 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* x1000 version: 1.0
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* x1000 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_DDRPHY_H__
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#define __HEADERGEN_DDRPHY_H__
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#include "macro.h"
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#define REG_DDRPHY_PIR jz_reg(DDRPHY_PIR)
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#define JA_DDRPHY_PIR (0xb3011000 + 0x4)
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#define JT_DDRPHY_PIR JIO_32_RW
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#define JN_DDRPHY_PIR DDRPHY_PIR
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#define JI_DDRPHY_PIR
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#define REG_DDRPHY_PGCR jz_reg(DDRPHY_PGCR)
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#define JA_DDRPHY_PGCR (0xb3011000 + 0x8)
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#define JT_DDRPHY_PGCR JIO_32_RW
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#define JN_DDRPHY_PGCR DDRPHY_PGCR
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#define JI_DDRPHY_PGCR
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#define REG_DDRPHY_PGSR jz_reg(DDRPHY_PGSR)
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#define JA_DDRPHY_PGSR (0xb3011000 + 0xc)
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#define JT_DDRPHY_PGSR JIO_32_RW
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#define JN_DDRPHY_PGSR DDRPHY_PGSR
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#define JI_DDRPHY_PGSR
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#define REG_DDRPHY_DLLGCR jz_reg(DDRPHY_DLLGCR)
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#define JA_DDRPHY_DLLGCR (0xb3011000 + 0x10)
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#define JT_DDRPHY_DLLGCR JIO_32_RW
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#define JN_DDRPHY_DLLGCR DDRPHY_DLLGCR
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#define JI_DDRPHY_DLLGCR
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#define REG_DDRPHY_ACDLLCR jz_reg(DDRPHY_ACDLLCR)
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#define JA_DDRPHY_ACDLLCR (0xb3011000 + 0x14)
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#define JT_DDRPHY_ACDLLCR JIO_32_RW
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#define JN_DDRPHY_ACDLLCR DDRPHY_ACDLLCR
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#define JI_DDRPHY_ACDLLCR
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#define REG_DDRPHY_PTR0 jz_reg(DDRPHY_PTR0)
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#define JA_DDRPHY_PTR0 (0xb3011000 + 0x18)
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#define JT_DDRPHY_PTR0 JIO_32_RW
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#define JN_DDRPHY_PTR0 DDRPHY_PTR0
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#define JI_DDRPHY_PTR0
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#define REG_DDRPHY_PTR1 jz_reg(DDRPHY_PTR1)
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#define JA_DDRPHY_PTR1 (0xb3011000 + 0x1c)
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#define JT_DDRPHY_PTR1 JIO_32_RW
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#define JN_DDRPHY_PTR1 DDRPHY_PTR1
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#define JI_DDRPHY_PTR1
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#define REG_DDRPHY_PTR2 jz_reg(DDRPHY_PTR2)
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#define JA_DDRPHY_PTR2 (0xb3011000 + 0x20)
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#define JT_DDRPHY_PTR2 JIO_32_RW
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#define JN_DDRPHY_PTR2 DDRPHY_PTR2
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#define JI_DDRPHY_PTR2
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#define REG_DDRPHY_ACIOCR jz_reg(DDRPHY_ACIOCR)
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#define JA_DDRPHY_ACIOCR (0xb3011000 + 0x24)
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#define JT_DDRPHY_ACIOCR JIO_32_RW
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#define JN_DDRPHY_ACIOCR DDRPHY_ACIOCR
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#define JI_DDRPHY_ACIOCR
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#define REG_DDRPHY_DXCCR jz_reg(DDRPHY_DXCCR)
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#define JA_DDRPHY_DXCCR (0xb3011000 + 0x28)
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#define JT_DDRPHY_DXCCR JIO_32_RW
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#define JN_DDRPHY_DXCCR DDRPHY_DXCCR
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#define JI_DDRPHY_DXCCR
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#define REG_DDRPHY_DSGCR jz_reg(DDRPHY_DSGCR)
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#define JA_DDRPHY_DSGCR (0xb3011000 + 0x2c)
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#define JT_DDRPHY_DSGCR JIO_32_RW
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#define JN_DDRPHY_DSGCR DDRPHY_DSGCR
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#define JI_DDRPHY_DSGCR
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#define REG_DDRPHY_DCR jz_reg(DDRPHY_DCR)
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#define JA_DDRPHY_DCR (0xb3011000 + 0x30)
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#define JT_DDRPHY_DCR JIO_32_RW
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#define JN_DDRPHY_DCR DDRPHY_DCR
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#define JI_DDRPHY_DCR
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#define REG_DDRPHY_DTPR0 jz_reg(DDRPHY_DTPR0)
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#define JA_DDRPHY_DTPR0 (0xb3011000 + 0x34)
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#define JT_DDRPHY_DTPR0 JIO_32_RW
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#define JN_DDRPHY_DTPR0 DDRPHY_DTPR0
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#define JI_DDRPHY_DTPR0
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#define REG_DDRPHY_DTPR1 jz_reg(DDRPHY_DTPR1)
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#define JA_DDRPHY_DTPR1 (0xb3011000 + 0x38)
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#define JT_DDRPHY_DTPR1 JIO_32_RW
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#define JN_DDRPHY_DTPR1 DDRPHY_DTPR1
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#define JI_DDRPHY_DTPR1
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#define REG_DDRPHY_DTPR2 jz_reg(DDRPHY_DTPR2)
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#define JA_DDRPHY_DTPR2 (0xb3011000 + 0x3c)
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#define JT_DDRPHY_DTPR2 JIO_32_RW
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#define JN_DDRPHY_DTPR2 DDRPHY_DTPR2
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#define JI_DDRPHY_DTPR2
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#define REG_DDRPHY_MR0 jz_reg(DDRPHY_MR0)
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#define JA_DDRPHY_MR0 (0xb3011000 + 0x40)
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#define JT_DDRPHY_MR0 JIO_32_RW
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#define JN_DDRPHY_MR0 DDRPHY_MR0
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#define JI_DDRPHY_MR0
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#define REG_DDRPHY_MR1 jz_reg(DDRPHY_MR1)
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#define JA_DDRPHY_MR1 (0xb3011000 + 0x44)
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#define JT_DDRPHY_MR1 JIO_32_RW
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#define JN_DDRPHY_MR1 DDRPHY_MR1
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#define JI_DDRPHY_MR1
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#define REG_DDRPHY_MR2 jz_reg(DDRPHY_MR2)
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#define JA_DDRPHY_MR2 (0xb3011000 + 0x48)
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#define JT_DDRPHY_MR2 JIO_32_RW
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#define JN_DDRPHY_MR2 DDRPHY_MR2
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#define JI_DDRPHY_MR2
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#define REG_DDRPHY_MR3 jz_reg(DDRPHY_MR3)
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#define JA_DDRPHY_MR3 (0xb3011000 + 0x4c)
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#define JT_DDRPHY_MR3 JIO_32_RW
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#define JN_DDRPHY_MR3 DDRPHY_MR3
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#define JI_DDRPHY_MR3
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#define REG_DDRPHY_DTAR jz_reg(DDRPHY_DTAR)
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#define JA_DDRPHY_DTAR (0xb3011000 + 0x54)
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#define JT_DDRPHY_DTAR JIO_32_RW
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#define JN_DDRPHY_DTAR DDRPHY_DTAR
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#define JI_DDRPHY_DTAR
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#define REG_DDRPHY_DXGCR(_n1) jz_reg(DDRPHY_DXGCR(_n1))
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#define JA_DDRPHY_DXGCR(_n1) (0xb3011000 + 0x1c0 + (_n1) * 0x40)
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#define JT_DDRPHY_DXGCR(_n1) JIO_32_RW
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#define JN_DDRPHY_DXGCR(_n1) DDRPHY_DXGCR
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#define JI_DDRPHY_DXGCR(_n1) (_n1)
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#endif /* __HEADERGEN_DDRPHY_H__*/
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