2002-06-30 20:22:25 +00:00
|
|
|
/***************************************************************************
|
|
|
|
* __________ __ ___.
|
|
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
|
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
|
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
|
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
|
|
|
* \/ \/ \/ \/ \/
|
|
|
|
* $Id$
|
|
|
|
*
|
|
|
|
* Copyright (C) 2002 by Linus Nielsen Feltzing
|
|
|
|
*
|
|
|
|
* All files in this archive are subject to the GNU General Public License.
|
|
|
|
* See the file COPYING in the source tree root for full license agreement.
|
|
|
|
*
|
|
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
|
|
|
* KIND, either express or implied.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
#include "config.h"
|
2004-11-03 00:39:30 +00:00
|
|
|
#include "cpu.h"
|
2002-06-30 20:22:25 +00:00
|
|
|
#include "kernel.h"
|
|
|
|
#include "thread.h"
|
|
|
|
#include "adc.h"
|
|
|
|
|
2004-11-03 00:39:30 +00:00
|
|
|
#if CONFIG_CPU == SH7034
|
2004-09-21 08:59:36 +00:00
|
|
|
/**************************************************************************
|
|
|
|
** The A/D conversion is done every tick, in three steps:
|
|
|
|
**
|
|
|
|
** 1) On the tick interrupt, the conversion of channels 0-3 is started, and
|
|
|
|
** the A/D interrupt is enabled.
|
|
|
|
**
|
|
|
|
** 2) After the conversion is done (approx. 256*4 cycles later), an interrupt
|
|
|
|
** is generated at level 1, which is the same level as the tick interrupt
|
|
|
|
** itself. This interrupt will be pending until the tick interrupt is
|
|
|
|
** finished.
|
|
|
|
** When the A/D interrupt is finally served, it will read the results
|
|
|
|
** from the first conversion and start the conversion of channels 4-7.
|
|
|
|
**
|
|
|
|
** 3) When the conversion of channels 4-7 is finished, the interrupt is
|
|
|
|
** triggered again, and the results are read. This time, no new
|
|
|
|
** conversion is started, it will be done in the next tick interrupt.
|
|
|
|
**
|
|
|
|
** Thus, each channel will be updated HZ times per second.
|
|
|
|
**
|
|
|
|
*************************************************************************/
|
|
|
|
|
2004-01-20 11:57:50 +00:00
|
|
|
static int current_channel;
|
2002-06-30 20:22:25 +00:00
|
|
|
static unsigned short adcdata[NUM_ADC_CHANNELS];
|
|
|
|
|
|
|
|
static void adc_tick(void)
|
|
|
|
{
|
2004-09-21 08:59:36 +00:00
|
|
|
/* Start a conversion of channel group 0. This will trigger an interrupt,
|
|
|
|
and the interrupt handler will take care of group 1. */
|
2002-06-30 20:22:25 +00:00
|
|
|
|
2004-09-21 08:59:36 +00:00
|
|
|
current_channel = 0;
|
|
|
|
ADCSR = ADCSR_ADST | ADCSR_ADIE | ADCSR_SCAN | 3;
|
2002-06-30 20:22:25 +00:00
|
|
|
}
|
|
|
|
|
2004-09-21 08:59:36 +00:00
|
|
|
#pragma interrupt
|
|
|
|
void ADITI(void)
|
2002-06-30 20:22:25 +00:00
|
|
|
{
|
2004-09-21 08:59:36 +00:00
|
|
|
if(ADCSR & ADCSR_ADF)
|
2004-01-20 11:57:50 +00:00
|
|
|
{
|
2004-09-21 08:59:36 +00:00
|
|
|
ADCSR = 0;
|
2004-01-20 11:57:50 +00:00
|
|
|
|
2004-09-21 08:59:36 +00:00
|
|
|
if(current_channel == 0)
|
|
|
|
{
|
|
|
|
adcdata[0] = ADDRA >> 6;
|
|
|
|
adcdata[1] = ADDRB >> 6;
|
|
|
|
adcdata[2] = ADDRC >> 6;
|
|
|
|
adcdata[3] = ADDRD >> 6;
|
|
|
|
current_channel = 4;
|
|
|
|
|
|
|
|
/* Convert the next group */
|
|
|
|
ADCSR = ADCSR_ADST | ADCSR_ADIE | ADCSR_SCAN | 7;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
adcdata[4] = ADDRA >> 6;
|
|
|
|
adcdata[5] = ADDRB >> 6;
|
|
|
|
adcdata[6] = ADDRC >> 6;
|
|
|
|
adcdata[7] = ADDRD >> 6;
|
|
|
|
}
|
2004-01-20 11:57:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-09-21 08:59:36 +00:00
|
|
|
unsigned short adc_read(int channel)
|
|
|
|
{
|
|
|
|
return adcdata[channel];
|
|
|
|
}
|
|
|
|
|
2004-01-20 11:57:50 +00:00
|
|
|
void adc_init(void)
|
|
|
|
{
|
2004-09-21 08:59:36 +00:00
|
|
|
ADCR = 0x7f; /* No external trigger; other bits should be 1 according
|
|
|
|
to the manual... */
|
2004-01-20 11:57:50 +00:00
|
|
|
|
2004-09-21 08:59:36 +00:00
|
|
|
ADCSR = 0;
|
|
|
|
|
2004-01-20 11:57:50 +00:00
|
|
|
current_channel = 0;
|
|
|
|
|
2004-09-21 08:59:36 +00:00
|
|
|
/* Enable the A/D IRQ on level 1 */
|
|
|
|
IPRE = (IPRE & 0xf0ff) | 0x0100;
|
2003-07-16 21:07:53 +00:00
|
|
|
|
2002-06-30 20:22:25 +00:00
|
|
|
tick_add_task(adc_tick);
|
2004-09-24 22:26:16 +00:00
|
|
|
|
2004-10-01 06:05:22 +00:00
|
|
|
sleep(2); /* Ensure valid readings when adc_init returns */
|
2002-06-30 20:22:25 +00:00
|
|
|
}
|
2004-11-03 00:39:30 +00:00
|
|
|
#elif CONFIG_CPU == MCF5249
|
|
|
|
|
|
|
|
static unsigned char adcdata[NUM_ADC_CHANNELS];
|
|
|
|
|
|
|
|
#define CS_LO GPIO_OUT &= ~0x80
|
|
|
|
#define CS_HI GPIO_OUT |= 0x80
|
|
|
|
#define CLK_LO GPIO_OUT &= ~0x00400000
|
|
|
|
#define CLK_HI GPIO_OUT |= 0x00400000
|
|
|
|
#define DO (GPIO_READ & 0x80000000)
|
|
|
|
#define DI_LO GPIO_OUT &= ~0x00200000
|
|
|
|
#define DI_HI GPIO_OUT |= 0x00200000
|
|
|
|
|
|
|
|
/* delay loop */
|
|
|
|
#define DELAY do { int _x; for(_x=0;_x<10;_x++);} while (0)
|
|
|
|
|
|
|
|
unsigned char adc_scan(int channel)
|
|
|
|
{
|
|
|
|
unsigned char data = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
CS_LO;
|
|
|
|
|
|
|
|
DI_HI; /* Start bit */
|
|
|
|
DELAY;
|
|
|
|
CLK_HI;
|
|
|
|
DELAY;
|
|
|
|
CLK_LO;
|
|
|
|
|
|
|
|
DI_HI; /* Single channel */
|
|
|
|
DELAY;
|
|
|
|
CLK_HI;
|
|
|
|
DELAY;
|
|
|
|
CLK_LO;
|
|
|
|
|
|
|
|
if(channel & 1) /* LSB of channel number */
|
|
|
|
DI_HI;
|
|
|
|
else
|
|
|
|
DI_LO;
|
|
|
|
DELAY;
|
|
|
|
CLK_HI;
|
|
|
|
DELAY;
|
|
|
|
CLK_LO;
|
|
|
|
|
|
|
|
if(channel & 2) /* MSB of channel number */
|
|
|
|
DI_HI;
|
|
|
|
else
|
|
|
|
DI_LO;
|
|
|
|
DELAY;
|
|
|
|
CLK_HI;
|
|
|
|
DELAY;
|
|
|
|
CLK_LO;
|
|
|
|
|
|
|
|
DELAY;
|
|
|
|
|
|
|
|
for(i = 0;i < 8;i++) /* 8 bits of data */
|
|
|
|
{
|
|
|
|
CLK_HI;
|
|
|
|
DELAY;
|
|
|
|
CLK_LO;
|
|
|
|
DELAY;
|
|
|
|
data <<= 1;
|
|
|
|
data |= DO?1:0;
|
|
|
|
}
|
|
|
|
|
|
|
|
CS_HI;
|
|
|
|
|
|
|
|
return data;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned short adc_read(int channel)
|
|
|
|
{
|
|
|
|
return adcdata[channel];
|
|
|
|
}
|
|
|
|
|
2004-11-18 23:23:47 +00:00
|
|
|
static int adc_counter;
|
|
|
|
|
|
|
|
static void adc_tick(void)
|
|
|
|
{
|
|
|
|
if(++adc_counter == HZ)
|
|
|
|
{
|
|
|
|
adc_counter = 0;
|
|
|
|
adcdata[ADC_BATTERY] = adc_scan(ADC_BATTERY);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-11-03 00:39:30 +00:00
|
|
|
void adc_init(void)
|
|
|
|
{
|
|
|
|
GPIO_FUNCTION |= 0x80600080; /* GPIO7: CS
|
|
|
|
GPIO21: Data In (to the ADC)
|
|
|
|
GPIO22: CLK
|
|
|
|
GPIO31: Data Out (from the ADC) */
|
|
|
|
GPIO_ENABLE |= 0x00600080;
|
|
|
|
GPIO_OUT |= 0x80; /* CS high */
|
|
|
|
GPIO_OUT &= ~0x00400000; /* CLK low */
|
2004-11-18 23:23:47 +00:00
|
|
|
|
|
|
|
tick_add_task(adc_tick);
|
|
|
|
|
|
|
|
adcdata[3] = adc_scan(3);
|
2004-11-03 00:39:30 +00:00
|
|
|
}
|
|
|
|
|
2005-01-09 23:26:39 +00:00
|
|
|
#elif CONFIG_CPU == TCC730
|
|
|
|
|
|
|
|
|
|
|
|
/**************************************************************************
|
|
|
|
**
|
|
|
|
** Each channel will be updated HZ/CHANNEL_ORDER_SIZE times per second.
|
|
|
|
**
|
|
|
|
*************************************************************************/
|
|
|
|
|
|
|
|
static int current_channel;
|
|
|
|
static int current_channel_idx;
|
|
|
|
static unsigned short adcdata[NUM_ADC_CHANNELS];
|
|
|
|
|
|
|
|
#define CHANNEL_ORDER_SIZE 2
|
|
|
|
static int channel_order[CHANNEL_ORDER_SIZE] = {6,7};
|
|
|
|
|
|
|
|
static void adc_tick(void)
|
|
|
|
{
|
|
|
|
if (ADCON & (1 << 3)) {
|
|
|
|
/* previous conversion finished? */
|
|
|
|
adcdata[current_channel] = ADDATA >> 6;
|
|
|
|
if (++current_channel_idx >= CHANNEL_ORDER_SIZE)
|
|
|
|
current_channel_idx = 0;
|
|
|
|
current_channel = channel_order[current_channel_idx];
|
|
|
|
int adcon = (current_channel << 4) | 1;
|
|
|
|
ADCON = adcon;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned short adc_read(int channel)
|
|
|
|
{
|
|
|
|
return adcdata[channel];
|
|
|
|
}
|
|
|
|
|
|
|
|
void adc_init(void)
|
|
|
|
{
|
|
|
|
current_channel_idx = 0;
|
|
|
|
current_channel = channel_order[current_channel_idx];
|
|
|
|
|
|
|
|
ADCON = (current_channel << 4) | 1;
|
|
|
|
|
|
|
|
tick_add_task(adc_tick);
|
|
|
|
|
|
|
|
sleep(2); /* Ensure valid readings when adc_init returns */
|
|
|
|
}
|
|
|
|
|
2004-11-03 00:39:30 +00:00
|
|
|
#endif
|