103 lines
4.4 KiB
C
103 lines
4.4 KiB
C
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: $
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*
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* Copyright (C) 2009 by Karl Kurbjun
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#define M66591_REG(addr) (*(volatile unsigned short *) \
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((unsigned char *) M66591_BASE + (addr)) )
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/* Interrupt handler routine, visible for target handler */
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void USB_DEVICE(void);
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/* Register offsets */
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#define M66591_TRN_CTRL M66591_REG(0x00) /* pg 14 */
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#define M66591_TRN_LNSTAT M66591_REG(0x02) /* pg 16 */
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#define M66591_HSFS M66591_REG(0x04) /* pg 17 */
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#define M66591_TESTMODE M66591_REG(0x06) /* pg 18 */
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#define M66591_PIN_CFG0 M66591_REG(0x08) /* pg 19 */
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#define M66591_PIN_CFG1 M66591_REG(0x0A) /* pg 20 */
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#define M66591_PIN_CFG2 M66591_REG(0x0C) /* pg 21 */
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#define M66591_CPORT M66591_REG(0x14) /* pg 23 */
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#define M66591_DPORT M66591_REG(0x18) /* pg 24 */
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#define M66591_DCP_CTRLEN M66591_REG(0x26) /* pg 25 */
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#define M66591_CPORT_CTRL0 M66591_REG(0x28) /* pg 26 */
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#define M66591_CPORT_CTRL1 M66591_REG(0x2C) /* pg 28 */
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#define M66591_CPORT_CTRL2 M66591_REG(0x2E) /* pg 30 */
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#define M66591_DPORT_CTRL0 M66591_REG(0x30) /* pg 31 */
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#define M66591_DPORT_CTRL1 M66591_REG(0x34) /* pg 34 */
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#define M66591_DPORT_CTRL2 M66591_REG(0x36) /* pg 36 */
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#define M66591_INTCFG_MAIN M66591_REG(0x40) /* pg 37 */
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#define M66591_INTCFG_OUT M66591_REG(0x42) /* pg 40 */
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#define M66591_INTCFG_RDY M66591_REG(0x44) /* pg 41 */
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#define M66591_INTCFG_NRDY M66591_REG(0x48) /* pg 42 */
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#define M66591_INTCFG_EMP M66591_REG(0x4C) /* pg 43 */
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#define M66591_INTSTAT_MAIN M66591_REG(0x60) /* pg 44 */
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#define M66591_INTSTAT_RDY M66591_REG(0x64) /* pg 48 */
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#define M66591_INTSTAT_NRDY M66591_REG(0x68) /* pg 50 */
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#define M66591_INTSTAT_EMP M66591_REG(0x6C) /* pg 53 */
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#define M66591_USB_ADDRESS M66591_REG(0x74) /* pg 56 */
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#define M66591_USB_REQ0 M66591_REG(0x78) /* pg 57 */
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#define M66591_USB_REQ1 M66591_REG(0x7A) /* pg 58 */
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#define M66591_USB_REQ2 M66591_REG(0x7C) /* pg 59 */
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#define M66591_USB_REQ3 M66591_REG(0x7E) /* pg 60 */
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#define M66591_DCP_CNTMD M66591_REG(0x82) /* pg 61 */
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#define M66591_DCP_MXPKSZ M66591_REG(0x84) /* pg 62 */
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#define M66591_DCPCTRL M66591_REG(0x88) /* pg 63 */
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#define M66591_PIPE_CFGSEL M66591_REG(0x8C) /* pg 65 */
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#define M66591_PIPE_CFGWND M66591_REG(0x90) /* pg 66 */
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#define M66591_PIPECTRL1 M66591_REG(0xA0) /* pg 69 */
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#define M66591_PIPECTRL2 M66591_REG(0xA2) /* pg 69 */
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#define M66591_PIPECTRL3 M66591_REG(0xA4) /* pg 69 */
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#define M66591_PIPECTRL4 M66591_REG(0xA6) /* pg 69 */
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#define M66591_PIPECTRL5 M66591_REG(0xA8) /* pg 71 */
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#define M66591_PIPECTRL6 M66591_REG(0xAA) /* pg 71 */
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/* These defines are used for CTRL register handshake setup
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* They are used on the following registers:
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* DCPCTRL and PIPECTRL(1-6)
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*/
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#define PIPE_SHAKE_NAK 0x00
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#define PIPE_SHAKE_BUF 0x01
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#define PIPE_SHAKE_STALL 0x02
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/* These defines are used for the control transfer stage status */
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#define CTRL_IDLE 0x00 /* Idle Stage */
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#define CTRL_RTDS 0x01 /* Read transfer data stage */
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#define CTRL_RTSS 0x02 /* Read transfer status stage */
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#define CTRL_WTDS 0x03 /* Write transfer data stage */
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#define CTRL_WTSS 0x04 /* Write transfer status stage */
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#define CTRL_WTND 0x05 /* Write transfer no data stage */
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#define CTRL_TRER 0x06 /* Transmit error stage */
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