7510335fc4
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17213 a1c6a512-1295-4272-9138-f99709370657
301 lines
9.7 KiB
C
301 lines
9.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "cpu.h"
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#include "mmu-arm.h"
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#include "panic.h"
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void __attribute__((naked)) ttb_init(void) {
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asm volatile
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(
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"mcr p15, 0, %[ttbB], c2, c0, 0 \n" /* Set the TTB base address */
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"mcr p15, 0, %[ffff], c3, c0, 0 \n" /* Set all domains to manager status */
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"bx lr \n"
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:
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: [ttbB] "r" (TTB_BASE),
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[ffff] "r" (0xFFFFFFFF)
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);
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}
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void __attribute__((naked)) map_section(unsigned int pa, unsigned int va, int mb, int flags) {
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#if 0 /* This code needs to be fixed and the C needs to be replaced to ensure that stack is not used */
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asm volatile
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(
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/* pa &= (-1 << 20); // align to 1MB */
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"mov r0, r0, lsr #20 \n"
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"mov r0, r0, lsl #20 \n"
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/* pa |= (flags | 0x412);
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* bit breakdown:
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* 10: superuser - r/w, user - no access
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* 4: should be "1"
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* 3,2: Cache flags (flags (r3))
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* 1: Section signature
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*/
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"orr r0, r0, r3 \n"
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"orr r0, r0, #0x410 \n"
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"orr r0, r0, #0x2 \n"
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:
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:
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);
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register int *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */
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asm volatile
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(
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/* unsigned int* ttbPtr = TTB_BASE + (va >> 20);
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* sections are 1MB size
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*/
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"mov r1, r1, lsr #20 \n"
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"add r1, %[ttbB], r1, lsl #0x2 \n"
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/* Add MB to pa, flags are already present in pa, but addition
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* should not effect them
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*
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* #define MB (1 << 20)
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* for( ; mb>0; mb--, pa += MB)
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* {
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* *(ttbPtr++) = pa;
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* }
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* #undef MB
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*/
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"cmp r2, #0 \n"
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"bxle lr \n"
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"loop: \n"
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"str r0, [r1], #4 \n"
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"add r0, r0, #0x100000 \n"
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"sub r2, r2, #0x01 \n"
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"bne loop \n"
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"bx lr \n"
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:
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: [ttbB] "r" (ttb_base) /* This /HAS/ to be in r3 */
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);
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(void) pa;
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(void) va;
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(void) mb;
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(void) flags;
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#else
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pa &= (-1 << 20);
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pa |= (flags | 0x412);
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unsigned int* ttbPtr = TTB_BASE + (va >> 20);
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#define MB (1 << 20)
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for( ; mb>0; mb--, pa += MB)
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{
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*(ttbPtr++) = pa;
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}
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#undef MB
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#endif
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}
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void __attribute__((naked)) enable_mmu(void) {
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asm volatile(
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"mov r0, #0 \n"
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"mcr p15, 0, r0, c8, c7, 0 \n" /* invalidate TLB */
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"mcr p15, 0, r0, c7, c7,0 \n" /* invalidate both icache and dcache */
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"mrc p15, 0, r0, c1, c0, 0 \n"
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"orr r0, r0, #1 \n" /* enable mmu bit, icache and dcache */
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"orr r0, r0, #1<<2 \n" /* enable dcache */
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"orr r0, r0, #1<<12 \n" /* enable icache */
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"mcr p15, 0, r0, c1, c0, 0 \n"
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"nop \n"
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"nop \n"
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"nop \n"
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"nop \n"
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"bx lr \n"
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:
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:
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: "r0"
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);
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}
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#if CONFIG_CPU == IMX31L
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void __attribute__((naked)) invalidate_dcache_range(const void *base, unsigned int size)
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{
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asm volatile(
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"add r1, r1, r0 \n"
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"mov r2, #0 \n"
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"mcrr p15, 0, r1, r0, c14 \n" /* Clean and invalidate dcache range */
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"mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
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"bx lr \n"
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);
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(void)base; (void)size;
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}
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#else
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/* Invalidate DCache for this range */
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/* Will do write back */
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void invalidate_dcache_range(const void *base, unsigned int size) {
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unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/
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unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */
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asm volatile(
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"inv_start: \n"
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"mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"add %0, %0, #32 \n"
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"cmp %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"bne inv_start \n"
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"mov %0, #0\n"
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"mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
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: : "r" (addr), "r" (end)
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);
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}
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#endif
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#if CONFIG_CPU == IMX31L
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void __attribute__((naked)) clean_dcache_range(const void *base, unsigned int size)
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{
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asm volatile(
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"add r1, r1, r0 \n"
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"mov r2, #0 \n"
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"mcrr p15, 0, r1, r0, c12 \n" /* Clean dcache range */
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"mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
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"bx lr \n"
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);
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(void)base; (void)size;
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}
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#else
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/* clean DCache for this range */
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/* forces DCache writeback for the specified range */
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void clean_dcache_range(const void *base, unsigned int size) {
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unsigned int addr = (int) base;
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unsigned int end = addr+size+32;
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asm volatile(
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"bic %0, %0, #31 \n"
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"clean_start: \n"
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"mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"add %0, %0, #32 \n"
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"cmp %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"blo clean_start \n"
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"mov %0, #0\n"
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"mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
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: : "r" (addr), "r" (end));
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}
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#endif
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#if CONFIG_CPU == IMX31L
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void __attribute__((naked)) dump_dcache_range(const void *base, unsigned int size)
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{
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asm volatile(
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"add r1, r1, r0 \n"
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"mcrr p15, 0, r1, r0, c6 \n"
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"bx lr \n"
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);
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(void)base; (void)size;
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}
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#else
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/* Dump DCache for this range */
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/* Will *NOT* do write back */
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void dump_dcache_range(const void *base, unsigned int size) {
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unsigned int addr = (int) base;
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unsigned int end = addr+size;
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asm volatile(
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"tst %0, #31 \n" /* Check to see if low five bits are set */
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"bic %0, %0, #31 \n" /* Clear them */
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line, if those bits were set */
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"add %0, %0, #32 \n" /* Move to the next cache line */
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"tst %1, #31 \n" /* Check last line for bits set */
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"bic %1, %1, #31 \n" /* Clear those bits */
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"mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */
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"dump_start: \n"
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"mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */
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"add %0, %0, #32 \n" /* Next cache line */
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"cmp %0, %1 \n"
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"bne dump_start \n"
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"dump_end: \n"
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"mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
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: : "r" (addr), "r" (end));
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}
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#endif
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#if CONFIG_CPU == IMX31L
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void __attribute__((naked)) clean_dcache(void)
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{
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asm volatile (
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/* Clean entire data cache */
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"mov r0, #0 \n"
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"mcr p15, 0, r0, c7, c10, 0 \n"
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"bx lr \n"
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);
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}
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#else
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/* Cleans entire DCache */
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void clean_dcache(void)
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{
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unsigned int index, addr, low;
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for(index = 0; index <= 63; index++)
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{
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for(low = 0;low <= 7; low++)
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{
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addr = (index << 26) | (low << 5);
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asm volatile
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(
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"mcr p15, 0, %[addr], c7, c10, 2 \n" /* Clean this entry by index */
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:
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: [addr] "r" (addr)
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);
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}
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}
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}
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#endif
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