35f23267bf
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15302 a1c6a512-1295-4272-9138-f99709370657
337 lines
12 KiB
C
337 lines
12 KiB
C
/*
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libdemac - A Monkey's Audio decoder
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$Id$
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Copyright (C) Dave Chapman 2007
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Coldfire vector math copyright (C) 2007 Jens Arnold
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
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*/
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/* This version fetches data as 32 bit words, and *recommends* v1 to be
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* 32 bit aligned, otherwise performance will suffer. */
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static inline void vector_add(int16_t* v1, int16_t* v2)
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{
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#if ORDER > 16
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int cnt = ORDER>>4;
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#endif
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#define ADDHALFREGS(s1, sum) /* Add register halves straight. */ \
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"move.l " #s1 ", %%d4 \n" /* 's1' can be an A or D reg. */ \
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"add.l " #sum ", " #s1 "\n" /* 'sum' must be a D reg. */ \
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"clr.w %%d4 \n" /* 's1' and %%d4 are clobbered! */ \
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"add.l %%d4 , " #sum "\n" \
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"move.w " #s1 ", " #sum "\n"
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#define ADDHALFXREGS(s1, s2, sum) /* Add register halves across. */ \
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"clr.w " #sum " \n" /* Needs 'sum' pre-swapped, swaps */ \
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"add.l " #s1 ", " #sum "\n" /* 's2', and clobbers 's1'. */ \
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"swap " #s2 " \n" /* 's1' can be an A or D reg. */ \
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"add.l " #s2 ", " #s1 "\n" /* 'sum' and 's2' must be D regs. */ \
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"move.w " #s1 ", " #sum "\n"
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asm volatile (
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"move.l %[v2], %%d0 \n"
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"and.l #2, %%d0 \n"
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"jeq 20f \n"
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"10: \n"
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"move.w (%[v2])+, %%d0 \n"
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"swap %%d0 \n"
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"1: \n"
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"movem.l (%[v1]), %%a0-%%a3 \n"
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"movem.l (%[v2]), %%d1-%%d4 \n"
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ADDHALFXREGS(%%a0, %%d1, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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ADDHALFXREGS(%%a1, %%d2, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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ADDHALFXREGS(%%a2, %%d3, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFXREGS(%%a3, %%d4, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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"lea.l (16, %[v2]), %[v2] \n"
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"move.l %%d4, %%d0 \n"
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"movem.l (%[v1]), %%a0-%%a3 \n"
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"movem.l (%[v2]), %%d1-%%d4 \n"
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ADDHALFXREGS(%%a0, %%d1, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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ADDHALFXREGS(%%a1, %%d2, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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ADDHALFXREGS(%%a2, %%d3, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFXREGS(%%a3, %%d4, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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#if ORDER > 16
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"lea.l (16, %[v2]), %[v2] \n"
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"move.l %%d4, %%d0 \n"
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"subq.l #1, %[cnt] \n"
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"jne 1b \n"
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#endif
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"jra 99f \n"
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"20: \n"
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"1: \n"
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"movem.l (%[v2]), %%a0-%%a3 \n"
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"movem.l (%[v1]), %%d0-%%d3 \n"
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ADDHALFREGS(%%a0, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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ADDHALFREGS(%%a1, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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ADDHALFREGS(%%a2, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%a3, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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"lea.l (16, %[v2]), %[v2] \n"
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"movem.l (%[v2]), %%a0-%%a3 \n"
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"movem.l (%[v1]), %%d0-%%d3 \n"
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ADDHALFREGS(%%a0, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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ADDHALFREGS(%%a1, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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ADDHALFREGS(%%a2, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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ADDHALFREGS(%%a3, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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#if ORDER > 16
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"lea.l (16, %[v2]), %[v2] \n"
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"subq.l #1, %[cnt] \n"
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"jne 1b \n"
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#endif
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"99: \n"
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: /* outputs */
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#if ORDER > 16
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[cnt]"+d"(cnt),
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#endif
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[v1] "+a"(v1),
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[v2] "+a"(v2)
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: /* inputs */
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: /* clobbers */
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"d0", "d1", "d2", "d3", "d4",
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"a0", "a1", "a2", "a3", "memory"
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);
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}
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/* This version fetches data as 32 bit words, and *recommends* v1 to be
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* 32 bit aligned, otherwise performance will suffer. */
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static inline void vector_sub(int16_t* v1, int16_t* v2)
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{
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#if ORDER > 16
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int cnt = ORDER>>4;
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#endif
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#define SUBHALFREGS(min, sub, dif) /* Subtract register halves straight. */ \
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"move.l " #min ", " #dif "\n" /* 'min' can be an A or D reg */ \
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"sub.l " #sub ", " #min "\n" /* 'sub' and 'dif' must be D regs */ \
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"clr.w " #sub "\n" /* 'min' and 'sub' are clobbered! */ \
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"sub.l " #sub ", " #dif "\n" \
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"move.w " #min ", " #dif "\n"
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#define SUBHALFXREGS(min, s2, s1d) /* Subtract register halves across. */ \
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"clr.w " #s1d "\n" /* Needs 's1d' pre-swapped, swaps */ \
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"sub.l " #s1d ", " #min "\n" /* 's2' and clobbers 'min'. */ \
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"move.l " #min ", " #s1d "\n" /* 'min' can be an A or D reg, */ \
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"swap " #s2 "\n" /* 's2' and 's1d' must be D regs. */ \
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"sub.l " #s2 ", " #min "\n" \
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"move.w " #min ", " #s1d "\n"
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asm volatile (
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"move.l %[v2], %%d0 \n"
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"and.l #2, %%d0 \n"
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"jeq 20f \n"
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"10: \n"
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"move.w (%[v2])+, %%d0 \n"
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"swap %%d0 \n"
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"1: \n"
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"movem.l (%[v2]), %%d1-%%d4 \n"
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"movem.l (%[v1]), %%a0-%%a3 \n"
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SUBHALFXREGS(%%a0, %%d1, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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SUBHALFXREGS(%%a1, %%d2, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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SUBHALFXREGS(%%a2, %%d3, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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SUBHALFXREGS(%%a3, %%d4, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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"lea.l (16, %[v2]), %[v2] \n"
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"move.l %%d4, %%d0 \n"
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"movem.l (%[v2]), %%d1-%%d4 \n"
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"movem.l (%[v1]), %%a0-%%a3 \n"
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SUBHALFXREGS(%%a0, %%d1, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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SUBHALFXREGS(%%a1, %%d2, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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SUBHALFXREGS(%%a2, %%d3, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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SUBHALFXREGS(%%a3, %%d4, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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#if ORDER > 16
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"lea.l (16, %[v2]), %[v2] \n"
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"move.l %%d4, %%d0 \n"
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"subq.l #1, %[cnt] \n"
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"bne.w 1b \n"
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#endif
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"jra 99f \n"
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"20: \n"
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"1: \n"
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"movem.l (%[v2]), %%d1-%%d4 \n"
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"movem.l (%[v1]), %%a0-%%a3 \n"
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SUBHALFREGS(%%a0, %%d1, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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SUBHALFREGS(%%a1, %%d2, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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SUBHALFREGS(%%a2, %%d3, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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SUBHALFREGS(%%a3, %%d4, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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"lea.l (16, %[v2]), %[v2] \n"
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"movem.l (%[v2]), %%d1-%%d4 \n"
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"movem.l (%[v1]), %%a0-%%a3 \n"
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SUBHALFREGS(%%a0, %%d1, %%d0)
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"move.l %%d0, (%[v1])+ \n"
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SUBHALFREGS(%%a1, %%d2, %%d1)
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"move.l %%d1, (%[v1])+ \n"
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SUBHALFREGS(%%a2, %%d3, %%d2)
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"move.l %%d2, (%[v1])+ \n"
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SUBHALFREGS(%%a3, %%d4, %%d3)
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"move.l %%d3, (%[v1])+ \n"
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#if ORDER > 16
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"lea.l (16, %[v2]), %[v2] \n"
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"subq.l #1, %[cnt] \n"
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"bne.w 1b \n"
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#endif
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"99: \n"
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: /* outputs */
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#if ORDER > 16
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[cnt]"+d"(cnt),
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#endif
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[v1] "+a"(v1),
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[v2] "+a"(v2)
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: /* inputs */
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: /* clobbers */
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"d0", "d1", "d2", "d3", "d4",
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"a0", "a1", "a2", "a3", "memory"
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);
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}
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#define PREPARE_SCALARPRODUCT coldfire_set_macsr(0); /* signed integer mode */
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/* This version fetches data as 32 bit words, and *recommends* v1 to be
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* 32 bit aligned, otherwise performance will suffer. It also needs EMAC
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* in signed integer mode - call above macro before use. */
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static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
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{
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int res = 0;
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#if ORDER > 32
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int cnt = ORDER>>5;
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#endif
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#define MACBLOCK4 \
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"mac.w %%d0u, %%d1u, (%[v1])+, %%d2, %%acc0\n" \
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"mac.w %%d0l, %%d1l, (%[v2])+, %%d1, %%acc0\n" \
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"mac.w %%d2u, %%d1u, (%[v1])+, %%d0, %%acc0\n" \
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"mac.w %%d2l, %%d1l, (%[v2])+, %%d1, %%acc0\n"
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#define MACBLOCK4_U2 \
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"mac.w %%d0u, %%d1l, (%[v2])+, %%d1, %%acc0\n" \
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"mac.w %%d0l, %%d1u, (%[v1])+, %%d0, %%acc0\n" \
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"mac.w %%d0u, %%d1l, (%[v2])+, %%d1, %%acc0\n" \
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"mac.w %%d0l, %%d1u, (%[v1])+, %%d0, %%acc0\n"
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asm volatile (
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"move.l %[v2], %%d0 \n"
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"and.l #2, %%d0 \n"
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"jeq 20f \n"
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"10: \n"
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"move.l (%[v1])+, %%d0 \n"
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"move.w (%[v2])+, %%d1 \n"
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"1: \n"
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#if ORDER > 16
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MACBLOCK4_U2
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MACBLOCK4_U2
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MACBLOCK4_U2
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MACBLOCK4_U2
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#endif
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MACBLOCK4_U2
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MACBLOCK4_U2
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MACBLOCK4_U2
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"mac.w %%d0u, %%d1l, (%[v2])+, %%d1, %%acc0\n"
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"mac.w %%d0l, %%d1u, (%[v1])+, %%d0, %%acc0\n"
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"mac.w %%d0u, %%d1l, (%[v2])+, %%d1, %%acc0\n"
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#if ORDER > 32
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"mac.w %%d0l, %%d1u, (%[v1])+, %%d0, %%acc0\n"
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"subq.l #1, %[res] \n"
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"bne.w 1b \n"
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#else
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"mac.w %%d0l, %%d1u, %%acc0 \n"
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#endif
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"jra 99f \n"
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"20: \n"
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"move.l (%[v1])+, %%d0 \n"
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"move.l (%[v2])+, %%d1 \n"
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"1: \n"
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#if ORDER > 16
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MACBLOCK4
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MACBLOCK4
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MACBLOCK4
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MACBLOCK4
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#endif
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MACBLOCK4
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MACBLOCK4
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MACBLOCK4
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"mac.w %%d0u, %%d1u, (%[v1])+, %%d2, %%acc0\n"
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"mac.w %%d0l, %%d1l, (%[v2])+, %%d1, %%acc0\n"
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#if ORDER > 32
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"mac.w %%d2u, %%d1u, (%[v1])+, %%d0, %%acc0\n"
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"mac.w %%d2l, %%d1l, (%[v2])+, %%d1, %%acc0\n"
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"subq.l #1, %[res] \n"
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"bne.w 1b \n"
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#else
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"mac.w %%d2u, %%d1u, %%acc0 \n"
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"mac.w %%d2l, %%d1l, %%acc0 \n"
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#endif
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"99: \n"
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"movclr.l %%acc0, %[res] \n"
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: /* outputs */
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[v1]"+a"(v1),
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[v2]"+a"(v2),
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[res]"=d"(res)
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: /* inputs */
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#if ORDER > 32
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[cnt]"[res]"(cnt)
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#endif
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: /* clobbers */
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"d0", "d1", "d2"
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);
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return res;
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}
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