8983fcb5f2
Bootloader builds, normal does not. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20574 a1c6a512-1295-4272-9138-f99709370657
678 lines
38 KiB
C
678 lines
38 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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*
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* Copyright (C) 2009 by Jorge Pinto
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register */
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#define AT91C_MATRIX_RCA926I (0x1 << 0) /* (MATRIX) Remap Command for
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ARM926EJ-S Instruction Master */
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#define AT91C_MATRIX_RCA926D (0x1 << 1) /* (MATRIX) Remap Command for
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ARM926EJ-S Data Master */
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/* Register definition for MATRIX peripheral */
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#define AT91C_MATRIX_MCFG0 (*(volatile unsigned long*) 0xFFFFEE00) /*(MATRIX)
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Master Configuration Register 0 (ram96k) */
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#define AT91C_MATRIX_MCFG7 (*(volatile unsigned long*) 0xFFFFEE1C) /*(MATRIX)
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Master Configuration Register 7 (teak_prog) */
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#define AT91C_MATRIX_SCFG1 (*(volatile unsigned long*) 0xFFFFEE44) /*(MATRIX)
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Slave Configuration Register 1 (rom) */
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#define AT91C_MATRIX_MCFG4 (*(volatile unsigned long*) 0xFFFFEE10) /*(MATRIX)
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Master Configuration Register 4 (bridge) */
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#define AT91C_MATRIX_VERSION (*(volatile unsigned long*) 0xFFFFEFFC) /*(MATRIX)
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Version Register */
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#define AT91C_MATRIX_MCFG2 (*(volatile unsigned long*) 0xFFFFEE08) /*(MATRIX)
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Master Configuration Register 2 (hperiphs) */
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#define AT91C_MATRIX_PRBS0 (*(volatile unsigned long*) 0xFFFFEE84) /*(MATRIX)
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PRBS0 (ram0) */
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#define AT91C_MATRIX_SCFG3 (*(volatile unsigned long*) 0xFFFFEE4C) /*(MATRIX)
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Slave Configuration Register 3 (ebi) */
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#define AT91C_MATRIX_MCFG6 (*(volatile unsigned long*) 0xFFFFEE18) /*(MATRIX)
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Master Configuration Register 6 (ram16k) */
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#define AT91C_MATRIX_EBI (*(volatile unsigned long*) 0xFFFFEF1C) /*(MATRIX)
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Slave 3 (ebi) Special Function Register */
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#define AT91C_MATRIX_SCFG0 (*(volatile unsigned long*) 0xFFFFEE40) /*(MATRIX)
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Slave Configuration Register 0 (ram96k) */
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#define AT91C_MATRIX_PRAS0 (*(volatile unsigned long*) 0xFFFFEE80) /*(MATRIX)
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PRAS0 (ram0) */
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#define AT91C_MATRIX_MCFG3 (*(volatile unsigned long*) 0xFFFFEE0C) /*(MATRIX)
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Master Configuration Register 3 (ebi) */
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#define AT91C_MATRIX_PRAS1 (*(volatile unsigned long*) 0xFFFFEE88) /*(MATRIX)
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PRAS1 (ram1) */
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#define AT91C_MATRIX_PRAS2 (*(volatile unsigned long*) 0xFFFFEE90) /*(MATRIX)
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PRAS2 (ram2) */
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#define AT91C_MATRIX_SCFG2 (*(volatile unsigned long*) 0xFFFFEE48) /*(MATRIX)
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Slave Configuration Register 2 (hperiphs) */
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#define AT91C_MATRIX_MCFG5 (*(volatile unsigned long*) 0xFFFFEE14) /*(MATRIX)
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Master Configuration Register 5 (mailbox) */
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#define AT91C_MATRIX_MCFG1 (*(volatile unsigned long*) 0xFFFFEE04) /*(MATRIX)
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Master Configuration Register 1 (rom) */
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#define AT91C_MATRIX_MRCR (*(volatile unsigned long*) 0xFFFFEF00) /*(MATRIX)
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Master Remp Control Register */
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#define AT91C_MATRIX_PRBS2 (*(volatile unsigned long*) 0xFFFFEE94) /*(MATRIX)
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PRBS2 (ram2) */
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#define AT91C_MATRIX_SCFG4 (*(volatile unsigned long*) 0xFFFFEE50) /*(MATRIX)
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Slave Configuration Register 4 (bridge) */
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#define AT91C_MATRIX_TEAKCFG (*(volatile unsigned long*) 0xFFFFEF2C) /*(MATRIX)
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Slave 7 (teak_prog) Special Function Register */
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#define AT91C_MATRIX_PRBS1 (*(volatile unsigned long*) 0xFFFFEE8C) /*(MATRIX)
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PRBS1 (ram1) */
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/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
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/* - WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register ---- */
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#define AT91C_WDTC_WDRSTT (0x1 << 0) /* (WDTC) Watchdog Restart */
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#define AT91C_WDTC_KEY (0xFF << 24) /* (WDTC) Watchdog KEY Password */
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/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
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#define AT91C_WDTC_WDV (0xFFF << 0) /* (WDTC) Watchdog Timer Restart */
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#define AT91C_WDTC_WDFIEN (0x1 << 12) /* (WDTC) Watchdog Fault Interrupt
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Enable */
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#define AT91C_WDTC_WDRSTEN (0x1 << 13) /* (WDTC) Watchdog Reset Enable */
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#define AT91C_WDTC_WDRPROC (0x1 << 14) /* (WDTC) Watchdog Timer Restart */
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#define AT91C_WDTC_WDDIS (0x1 << 15) /* (WDTC) Watchdog Disable */
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#define AT91C_WDTC_WDD (0xFFF << 16) /* (WDTC) Watchdog Delta Value */
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#define AT91C_WDTC_WDDBGHLT (0x1 << 28) /* (WDTC) Watchdog Debug Halt */
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#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) /* (WDTC) Watchdog Idle Halt */
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/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register ----- */
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#define AT91C_WDTC_WDUNF (0x1 << 0) /* (WDTC) Watchdog Underflow */
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#define AT91C_WDTC_WDERR (0x1 << 1) /* (WDTC) Watchdog Error */
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/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
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/* - WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register ---- */
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#define AT91C_WDTC_WDRSTT (0x1 << 0) /* (WDTC) Watchdog Restart */
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#define AT91C_WDTC_KEY (0xFF << 24) /* (WDTC) Watchdog KEY Password */
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/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
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#define AT91C_WDTC_WDV (0xFFF << 0) /* (WDTC) Watchdog Timer Restart */
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#define AT91C_WDTC_WDFIEN (0x1 << 12) /* (WDTC) Watchdog Fault Interrupt
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Enable */
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#define AT91C_WDTC_WDRSTEN (0x1 << 13) /* (WDTC) Watchdog Reset Enable */
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#define AT91C_WDTC_WDRPROC (0x1 << 14) /* (WDTC) Watchdog Timer Restart */
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#define AT91C_WDTC_WDDIS (0x1 << 15) /* (WDTC) Watchdog Disable */
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#define AT91C_WDTC_WDD (0xFFF << 16) /* (WDTC) Watchdog Delta Value */
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#define AT91C_WDTC_WDDBGHLT (0x1 << 28) /* (WDTC) Watchdog Debug Halt */
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#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) /* (WDTC) Watchdog Idle Halt */
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/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register ----- */
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#define AT91C_WDTC_WDUNF (0x1 << 0) /* (WDTC) Watchdog Underflow */
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#define AT91C_WDTC_WDERR (0x1 << 1) /* (WDTC) Watchdog Error */
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/* Register definition for WDTC peripheral */
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#define AT91C_WDTC_WDCR (*(volatile unsigned long*) 0xFFFFFD40) /* (WDTC)
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Watchdog Control Register */
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#define AT91C_WDTC_WDSR (*(volatile unsigned long*) 0xFFFFFD48) /* (WDTC)
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Watchdog Status Register */
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#define AT91C_WDTC_WDMR (*(volatile unsigned long*) 0xFFFFFD44) /* (WDTC)
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Watchdog Mode Register */
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/* CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register */
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#define AT91C_CKGR_MOSCEN (0x1 << 0) /* (CKGR) Main Oscillator Enable */
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#define AT91C_CKGR_OSCBYPASS (0x1 << 1) /* (CKGR) Main Oscillator Bypass */
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#define AT91C_CKGR_OSCOUNT (0xFF << 8) /* (CKGR) Main Oscillator Start
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-up Time */
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/* CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register */
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#define AT91C_CKGR_MAINF (0xFFFF << 0) /* (CKGR) Main Clock Frequency */
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#define AT91C_CKGR_MAINRDY (0x1 << 16) /* (CKGR) Main Clock Ready */
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/* CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register */
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#define AT91C_CKGR_DIVA (0xFF << 0) /* (CKGR) Divider A Selected */
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#define AT91C_CKGR_DIVA_0 (0x0) /* (CKGR) Divider A output is 0 */
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#define AT91C_CKGR_DIVA_BYPASS (0x1) /* (CKGR) Divider A is bypassed */
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#define AT91C_CKGR_PLLACOUNT (0x3F << 8) /* (CKGR) PLL A Counter */
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#define AT91C_CKGR_OUTA (0x3 << 14) /* (CKGR) PLL A Output Frequency Range */
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#define AT91C_CKGR_OUTA_0 (0x0 << 14) /* (CKGR) Please
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refer to the PLLA datasheet */
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#define AT91C_CKGR_OUTA_1 (0x1 << 14) /* (CKGR) Please
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refer to the PLLA datasheet */
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#define AT91C_CKGR_OUTA_2 (0x2 << 14) /* (CKGR) Please
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refer to the PLLA datasheet */
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#define AT91C_CKGR_OUTA_3 (0x3 << 14) /* (CKGR) Please
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refer to the PLLA datasheet */
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#define AT91C_CKGR_MULA (0x7FF << 16) /* (CKGR) PLL A Multiplier */
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#define AT91C_CKGR_SRCA (0x1 << 29) /* (CKGR) */
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/* CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register */
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#define AT91C_CKGR_DIVB (0xFF << 0) /* (CKGR) Divider B Selected */
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#define AT91C_CKGR_DIVB_0 (0x0) /* (CKGR) Divider B output is 0 */
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#define AT91C_CKGR_DIVB_BYPASS (0x1) /* (CKGR) Divider B is bypassed */
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#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) /* (CKGR) PLL B Counter */
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#define AT91C_CKGR_OUTB (0x3 << 14) /* (CKGR) PLL B Output Frequency Range */
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#define AT91C_CKGR_OUTB_0 (0x0 << 14) /* (CKGR) Please
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refer to the PLLB datasheet */
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#define AT91C_CKGR_OUTB_1 (0x1 << 14) /* (CKGR) Please
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refer to the PLLB datasheet */
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#define AT91C_CKGR_OUTB_2 (0x2 << 14) /* (CKGR) Please
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refer to the PLLB datasheet */
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#define AT91C_CKGR_OUTB_3 (0x3 << 14) /* (CKGR) Please
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refer to the PLLB datasheet */
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#define AT91C_CKGR_MULB (0x7FF << 16) /* (CKGR) PLL B Multiplier */
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#define AT91C_CKGR_USBDIV (0x3 << 28) /* (CKGR) Divider for USB Clocks */
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#define AT91C_CKGR_USBDIV_0 (0x0 << 28) /* (CKGR)
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Divider output is PLL clock output */
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#define AT91C_CKGR_USBDIV_1 (0x1 << 28) /* (CKGR)
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Divider output is PLL clock output divided by 2 */
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#define AT91C_CKGR_USBDIV_2 (0x2 << 28) /* (CKGR)
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Divider output is PLL clock output divided by 4 */
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/* SOFTWARE API DEFINITION FOR Power Management Controler */
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/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register ----- */
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#define AT91C_PMC_PCK (0x1 << 0) /* (PMC) Processor Clock */
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#define AT91C_PMC_UHP (0x1 << 6) /* (PMC) USB Host Port Clock */
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#define AT91C_PMC_UDP (0x1 << 7) /* (PMC) USB Device Port Clock */
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#define AT91C_PMC_PCK0 (0x1 << 8) /* (PMC) Programmable Clock Output */
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#define AT91C_PMC_PCK1 (0x1 << 9) /* (PMC) Programmable Clock Output */
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#define AT91C_PMC_HCK0 (0x1 << 16) /* (PMC) AHB UHP Clock Output */
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#define AT91C_PMC_HCK1 (0x1 << 17) /* (PMC) AHB LCDC Clock Output */
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/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ----- */
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/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register ----- */
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/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
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/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register--- */
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/* -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- */
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/* -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- */
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/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
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#define AT91C_PMC_CSS (0x3 << 0) /* (PMC) Programmable Clock Selection */
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#define AT91C_PMC_CSS_SLOW_CLK (0x0) /* (PMC) Slow Clock is selected */
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#define AT91C_PMC_CSS_MAIN_CLK (0x1) /* (PMC) Main Clock is selected */
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#define AT91C_PMC_CSS_PLLA_CLK (0x2) /* (PMC) Clock from PLL A is selected */
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#define AT91C_PMC_CSS_PLLB_CLK (0x3) /* (PMC) Clock from PLL B is selected */
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#define AT91C_PMC_PRES (0x7 << 2) /* (PMC) Programmable Clock Prescaler */
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#define AT91C_PMC_PRES_CLK (0x0 << 2) /* (PMC) Selected clock */
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#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) /* (PMC) Selected clock
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divided by 2 */
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#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) /* (PMC) Selected clock
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divided by 4 */
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#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) /* (PMC) Selected clock
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divided by 8 */
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#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) /* (PMC) Selected clock
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divided by 16 */
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#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) /* (PMC) Selected clock
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divided by 32 */
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#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) /* (PMC) Selected clock
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divided by 64 */
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#define AT91C_PMC_MDIV (0x3 << 8) /* (PMC) Master Clock Divisionv */
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#define AT91C_PMC_MDIV_1 (0x0 << 8) /* (PMC) The master clock and the
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processor clock are the same */
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#define AT91C_PMC_MDIV_2 (0x1 << 8) /* (PMC) The processor clock is twice
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as fast as the master clock */
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#define AT91C_PMC_MDIV_3 (0x2 << 8) /* (PMC) The processor clock is four
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times faster than the master clock */
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/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register ----- */
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/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register ---- */
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#define AT91C_PMC_MOSCS (0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask*/
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#define AT91C_PMC_LOCKA (0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/
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Mask */
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#define AT91C_PMC_LOCKB (0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/
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Mask */
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#define AT91C_PMC_MCKRDY (0x1 << 3) /* (PMC) Master Clock Status/Enable/
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Disable/Mask */
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#define AT91C_PMC_PCK0RDY (0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/
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Disable/Mask */
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#define AT91C_PMC_PCK1RDY (0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/
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Disable/Mask */
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/* ---PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
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/* ------ PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
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#define AT91C_PMC_OSCSEL (0x1 << 7) /* (PMC) 32kHz Oscillator
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selection status */
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/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register ---- */
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/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
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/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
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#define AT91C_AIC_PRIOR (0x7 << 0) /* (AIC) Priority Level */
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#define AT91C_AIC_PRIOR_LOWEST (0x0) /* (AIC) Lowest priority
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level */
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#define AT91C_AIC_PRIOR_HIGHEST (0x7) /* (AIC) Highest
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priority level */
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#define AT91C_AIC_SRCTYPE (0x3 << 5) /* (AIC) Interrupt Source Type */
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#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) /* (AIC)
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Internal Sources Code Label Level Sensitive */
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#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) /* (AIC)
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Internal Sources Code Label Edge triggered */
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#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) /* (AIC)
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External Sources Code Label High-level Sensitive */
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#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) /* (AIC)
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External Sources Code Label Positive Edge triggered */
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/* - AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register ----- */
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#define AT91C_AIC_NFIQ (0x1 << 0) /* (AIC) NFIQ Status */
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#define AT91C_AIC_NIRQ (0x1 << 1) /* (AIC) NIRQ Status */
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/* - AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) ---- */
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#define AT91C_AIC_DCR_PROT (0x1 << 0) /* (AIC) Protection Mode */
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#define AT91C_AIC_DCR_GMSK (0x1 << 1) /* (AIC) General Mask */
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/* Register definition for AIC peripheral */
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#define AT91C_AIC_IVR (*(volatile unsigned long*) 0xFFFFF100) /* (AIC) IRQ
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Vector Register */
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#define AIC_IVR 0x00000100
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/* (AIC) Source Mode Register */
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#define AT91C_AIC_SMR(a) (*(volatile unsigned long*) (0xFFFFF000 + 4*(a)))
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#define AT91C_AIC_FVR (*(volatile unsigned long*) 0xFFFFF104) /* (AIC) FIQ
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Vector Register */
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#define AT91C_AIC_DCR (*(volatile unsigned long*) 0xFFFFF138) /* (AIC) Debug
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Control Register (Protect) */
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#define AT91C_AIC_EOICR (*(volatile unsigned long*) 0xFFFFF130) /* (AIC) End
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of Interrupt Command Register */
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#define AIC_EOICR 0x00000130
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/* (AIC) Source Vector Register */
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#define AT91C_AIC_SVR(a) (*(volatile unsigned long*) (0xFFFFF080 + 4*(a)))
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#define AT91C_AIC_FFSR (*(volatile unsigned long*) 0xFFFFF148) /* (AIC) Fast
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Forcing Status Register */
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#define AT91C_AIC_ICCR (*(volatile unsigned long*) 0xFFFFF128) /* (AIC)
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Interrupt Clear Command Register */
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#define AT91C_AIC_ISR (*(volatile unsigned long*) 0xFFFFF108) /* (AIC)
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Interrupt Status Register */
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#define AT91C_AIC_IMR (*(volatile unsigned long*) 0xFFFFF110) /* (AIC)
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Interrupt Mask Register */
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#define AT91C_AIC_IPR (*(volatile unsigned long*) 0xFFFFF10C) /* (AIC)
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Interrupt Pending Register */
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#define AT91C_AIC_FFER (*(volatile unsigned long*) 0xFFFFF140) /* (AIC)
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Fast Forcing Enable Register */
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#define AT91C_AIC_IECR (*(volatile unsigned long*) 0xFFFFF120) /* (AIC)
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Interrupt Enable Command Register */
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#define AT91C_AIC_ISCR (*(volatile unsigned long*) 0xFFFFF12C) /* (AIC)
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Interrupt Set Command Register */
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#define AT91C_AIC_FFDR (*(volatile unsigned long*) 0xFFFFF144) /* (AIC)
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Fast Forcing Disable Register */
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#define AT91C_AIC_CISR (*(volatile unsigned long*) 0xFFFFF114) /* (AIC)
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Core Interrupt Status Register */
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#define AT91C_AIC_IDCR (*(volatile unsigned long*) 0xFFFFF124) /* (AIC)
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Interrupt Disable Command Register */
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#define AT91C_AIC_SPU (*(volatile unsigned long*) 0xFFFFF134) /* (AIC)
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Spurious Vector Register */
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/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
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/* PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
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#define AT91C_PITC_PIV (0xFFFFF << 0) /* (PITC) Periodic Interval
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Value */
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#define AT91C_PITC_PITEN (0x1 << 24) /* (PITC) Periodic Interval Timer
|
|
Enabled */
|
|
#define AT91C_PITC_PITIEN (0x1 << 25) /* (PITC) Periodic Interval Timer
|
|
Interrupt Enable */
|
|
/* --- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register - */
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|
#define AT91C_PITC_PITS (0x1 << 0) /* (PITC) Periodic Interval Timer
|
|
Status */
|
|
/* - PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register ---- */
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|
#define AT91C_PITC_CPIV (0xFFFFF << 0) /* (PITC) Current Periodic
|
|
Interval Value */
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|
#define AT91C_PITC_PICNT (0xFFF << 20) /* (PITC) Periodic Interval Counter */
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/* PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register ---- */
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|
|
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/* Register definition for AIC peripheral */
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#define AT91C_AIC_IVR (*(volatile unsigned long*) 0xFFFFF100) /* (AIC) IRQ
|
|
Vector Register */
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|
#define AIC_IVR 0x00000100
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#define AT91C_AIC_EOICR (*(volatile unsigned long*) 0xFFFFF130) /* (AIC) End
|
|
of Interrupt Command Register */
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#define AIC_EOICR 0x00000130
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|
|
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/* Register definition for PIOA peripheral */
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#define AT91C_PIOA_ODR (*(volatile unsigned long*) 0xFFFFF414) /* (PIOA)
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|
Output Disable Registerr */
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#define AT91C_PIOA_SODR (*(volatile unsigned long*) 0xFFFFF430) /* (PIOA)
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|
Set Output Data Register */
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#define AT91C_PIOA_ISR (*(volatile unsigned long*) 0xFFFFF44C) /* (PIOA)
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|
Interrupt Status Register */
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#define AT91C_PIOA_ABSR (*(volatile unsigned long*) 0xFFFFF478) /* (PIOA)
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|
AB Select Status Register */
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#define AT91C_PIOA_IER (*(volatile unsigned long*) 0xFFFFF440) /* (PIOA)
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Interrupt Enable Register */
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#define AT91C_PIOA_PPUDR (*(volatile unsigned long*) 0xFFFFF460) /* (PIOA)
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Pull-up Disable Register */
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#define AT91C_PIOA_IMR (*(volatile unsigned long*) 0xFFFFF448) /* (PIOA)
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|
Interrupt Mask Register */
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#define AT91C_PIOA_PER (*(volatile unsigned long*) 0xFFFFF400) /* (PIOA)
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PIO Enable Register */
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#define AT91C_PIOA_IFDR (*(volatile unsigned long*) 0xFFFFF424) /* (PIOA)
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|
Input Filter Disable Register */
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#define AT91C_PIOA_OWDR (*(volatile unsigned long*) 0xFFFFF4A4) /* (PIOA)
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|
Output Write Disable Register */
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#define AT91C_PIOA_MDSR (*(volatile unsigned long*) 0xFFFFF458) /* (PIOA)
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|
Multi-driver Status Register */
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#define AT91C_PIOA_IDR (*(volatile unsigned long*) 0xFFFFF444) /* (PIOA)
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|
Interrupt Disable Register */
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#define AT91C_PIOA_ODSR (*(volatile unsigned long*) 0xFFFFF438) /* (PIOA)
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Output Data Status Register */
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#define AT91C_PIOA_PPUSR (*(volatile unsigned long*) 0xFFFFF468) /* (PIOA)
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Pull-up Status Register */
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#define AT91C_PIOA_OWSR (*(volatile unsigned long*) 0xFFFFF4A8) /* (PIOA)
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Output Write Status Register */
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#define AT91C_PIOA_BSR (*(volatile unsigned long*) 0xFFFFF474) /* (PIOA)
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Select B Register */
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#define AT91C_PIOA_OWER (*(volatile unsigned long*) 0xFFFFF4A0) /* (PIOA)
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|
Output Write Enable Register */
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#define AT91C_PIOA_IFER (*(volatile unsigned long*) 0xFFFFF420) /* (PIOA)
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|
Input Filter Enable Register */
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#define AT91C_PIOA_PDSR (*(volatile unsigned long*) 0xFFFFF43C) /* (PIOA)
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|
Pin Data Status Register */
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#define AT91C_PIOA_PPUER (*(volatile unsigned long*) 0xFFFFF464) /* (PIOA)
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|
Pull-up Enable Register */
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#define AT91C_PIOA_OSR (*(volatile unsigned long*) 0xFFFFF418) /* (PIOA)
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|
Output Status Register */
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#define AT91C_PIOA_ASR (*(volatile unsigned long*) 0xFFFFF470) /* (PIOA)
|
|
Select A Register */
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#define AT91C_PIOA_MDDR (*(volatile unsigned long*) 0xFFFFF454) /* (PIOA)
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|
Multi-driver Disable Register */
|
|
#define AT91C_PIOA_CODR (*(volatile unsigned long*) 0xFFFFF434) /* (PIOA)
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|
Clear Output Data Register */
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#define AT91C_PIOA_MDER (*(volatile unsigned long*) 0xFFFFF450) /* (PIOA)
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|
Multi-driver Enable Register */
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|
#define AT91C_PIOA_PDR (*(volatile unsigned long*) 0xFFFFF404) /* (PIOA)
|
|
PIO Disable Register */
|
|
#define AT91C_PIOA_IFSR (*(volatile unsigned long*) 0xFFFFF428) /* (PIOA)
|
|
Input Filter Status Register */
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#define AT91C_PIOA_OER (*(volatile unsigned long*) 0xFFFFF410) /* (PIOA)
|
|
Output Enable Register */
|
|
#define AT91C_PIOA_PSR (*(volatile unsigned long*) 0xFFFFF408) /* (PIOA)
|
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PIO Status Register */
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|
|
|
/* Register definition for PIOB peripheral */
|
|
#define AT91C_PIOB_OWDR (*(volatile unsigned long*) 0xFFFFF6A4) /* (PIOB)
|
|
Output Write Disable Register */
|
|
#define AT91C_PIOB_MDER (*(volatile unsigned long*) 0xFFFFF650) /* (PIOB)
|
|
Multi-driver Enable Register */
|
|
#define AT91C_PIOB_PPUSR (*(volatile unsigned long*) 0xFFFFF668) /* (PIOB)
|
|
Pull-up Status Register */
|
|
#define AT91C_PIOB_IMR (*(volatile unsigned long*) 0xFFFFF648) /* (PIOB)
|
|
Interrupt Mask Register */
|
|
#define AT91C_PIOB_ASR (*(volatile unsigned long*) 0xFFFFF670) /* (PIOB)
|
|
Select A Register */
|
|
#define AT91C_PIOB_PPUDR (*(volatile unsigned long*) 0xFFFFF660) /* (PIOB)
|
|
Pull-up Disable Register */
|
|
#define AT91C_PIOB_PSR (*(volatile unsigned long*) 0xFFFFF608) /* (PIOB)
|
|
PIO Status Register */
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#define AT91C_PIOB_IER (*(volatile unsigned long*) 0xFFFFF640) /* (PIOB)
|
|
Interrupt Enable Register */
|
|
#define AT91C_PIOB_CODR (*(volatile unsigned long*) 0xFFFFF634) /* (PIOB)
|
|
Clear Output Data Register */
|
|
#define AT91C_PIOB_OWER (*(volatile unsigned long*) 0xFFFFF6A0) /* (PIOB)
|
|
Output Write Enable Register */
|
|
#define AT91C_PIOB_ABSR (*(volatile unsigned long*) 0xFFFFF678) /* (PIOB)
|
|
AB Select Status Register */
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|
#define AT91C_PIOB_IFDR (*(volatile unsigned long*) 0xFFFFF624) /* (PIOB)
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|
Input Filter Disable Register */
|
|
#define AT91C_PIOB_PDSR (*(volatile unsigned long*) 0xFFFFF63C) /* (PIOB)
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|
Pin Data Status Register */
|
|
#define AT91C_PIOB_IDR (*(volatile unsigned long*) 0xFFFFF644) /* (PIOB)
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|
Interrupt Disable Register */
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|
#define AT91C_PIOB_OWSR (*(volatile unsigned long*) 0xFFFFF6A8) /* (PIOB)
|
|
Output Write Status Register */
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|
#define AT91C_PIOB_PDR (*(volatile unsigned long*) 0xFFFFF604) /* (PIOB)
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|
PIO Disable Register */
|
|
#define AT91C_PIOB_ODR (*(volatile unsigned long*) 0xFFFFF614) /* (PIOB)
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|
Output Disable Registerr */
|
|
#define AT91C_PIOB_IFSR (*(volatile unsigned long*) 0xFFFFF628) /* (PIOB)
|
|
Input Filter Status Register */
|
|
#define AT91C_PIOB_PPUER (*(volatile unsigned long*) 0xFFFFF664) /* (PIOB)
|
|
Pull-up Enable Register */
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#define AT91C_PIOB_SODR (*(volatile unsigned long*) 0xFFFFF630) /* (PIOB)
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|
Set Output Data Register */
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|
#define AT91C_PIOB_ISR (*(volatile unsigned long*) 0xFFFFF64C) /* (PIOB)
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Interrupt Status Register */
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#define AT91C_PIOB_ODSR (*(volatile unsigned long*) 0xFFFFF638) /* (PIOB)
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Output Data Status Register */
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#define AT91C_PIOB_OSR (*(volatile unsigned long*) 0xFFFFF618) /* (PIOB)
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Output Status Register */
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#define AT91C_PIOB_MDSR (*(volatile unsigned long*) 0xFFFFF658) /* (PIOB)
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Multi-driver Status Register */
|
|
#define AT91C_PIOB_IFER (*(volatile unsigned long*) 0xFFFFF620) /* (PIOB)
|
|
Input Filter Enable Register */
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#define AT91C_PIOB_BSR (*(volatile unsigned long*) 0xFFFFF674) /* (PIOB)
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Select B Register */
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#define AT91C_PIOB_MDDR (*(volatile unsigned long*) 0xFFFFF654) /* (PIOB)
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Multi-driver Disable Register */
|
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#define AT91C_PIOB_OER (*(volatile unsigned long*) 0xFFFFF610) /* (PIOB)
|
|
Output Enable Register */
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#define AT91C_PIOB_PER (*(volatile unsigned long*) 0xFFFFF600) /* (PIOB)
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PIO Enable Register */
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|
|
|
/* Register definition for PIOC peripheral */
|
|
#define AT91C_PIOC_OWDR (*(volatile unsigned long*) 0xFFFFF8A4) /* (PIOC)
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|
Output Write Disable Register */
|
|
#define AT91C_PIOC_SODR (*(volatile unsigned long*) 0xFFFFF830) /* (PIOC)
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|
Set Output Data Register */
|
|
#define AT91C_PIOC_PPUER (*(volatile unsigned long*) 0xFFFFF864) /* (PIOC)
|
|
Pull-up Enable Register */
|
|
#define AT91C_PIOC_CODR (*(volatile unsigned long*) 0xFFFFF834) /* (PIOC)
|
|
Clear Output Data Register */
|
|
#define AT91C_PIOC_PSR (*(volatile unsigned long*) 0xFFFFF808) /* (PIOC)
|
|
PIO Status Register */
|
|
#define AT91C_PIOC_PDR (*(volatile unsigned long*) 0xFFFFF804) /* (PIOC)
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|
PIO Disable Register */
|
|
#define AT91C_PIOC_ODR (*(volatile unsigned long*) 0xFFFFF814) /* (PIOC)
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|
Output Disable Register */
|
|
#define AT91C_PIOC_PPUSR (*(volatile unsigned long*) 0xFFFFF868) /* (PIOC)
|
|
Pull-up Status Register */
|
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#define AT91C_PIOC_ABSR (*(volatile unsigned long*) 0xFFFFF878) /* (PIOC)
|
|
AB Select Status Register */
|
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#define AT91C_PIOC_IFSR (*(volatile unsigned long*) 0xFFFFF828) /* (PIOC)
|
|
Input Filter Status Register */
|
|
#define AT91C_PIOC_OER (*(volatile unsigned long*) 0xFFFFF810) /* (PIOC)
|
|
Output Enable Register */
|
|
#define AT91C_PIOC_IMR (*(volatile unsigned long*) 0xFFFFF848) /* (PIOC)
|
|
Interrupt Mask Register */
|
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#define AT91C_PIOC_ASR (*(volatile unsigned long*) 0xFFFFF870) /* (PIOC)
|
|
Select A Register */
|
|
#define AT91C_PIOC_MDDR (*(volatile unsigned long*) 0xFFFFF854) /* (PIOC)
|
|
Multi-driver Disable Register */
|
|
#define AT91C_PIOC_OWSR (*(volatile unsigned long*) 0xFFFFF8A8) /* (PIOC)
|
|
Output Write Status Register */
|
|
#define AT91C_PIOC_PER (*(volatile unsigned long*) 0xFFFFF800) /* (PIOC)
|
|
PIO Enable Register */
|
|
#define AT91C_PIOC_IDR (*(volatile unsigned long*) 0xFFFFF844) /* (PIOC)
|
|
Interrupt Disable Register */
|
|
#define AT91C_PIOC_MDER (*(volatile unsigned long*) 0xFFFFF850) /* (PIOC)
|
|
Multi-driver Enable Register */
|
|
#define AT91C_PIOC_PDSR (*(volatile unsigned long*) 0xFFFFF83C) /* (PIOC)
|
|
Pin Data Status Register */
|
|
#define AT91C_PIOC_MDSR (*(volatile unsigned long*) 0xFFFFF858) /* (PIOC)
|
|
Multi-driver Status Register */
|
|
#define AT91C_PIOC_OWER (*(volatile unsigned long*) 0xFFFFF8A0) /* (PIOC)
|
|
Output Write Enable Register */
|
|
#define AT91C_PIOC_BSR (*(volatile unsigned long*) 0xFFFFF874) /* (PIOC)
|
|
Select B Register */
|
|
#define AT91C_PIOC_PPUDR (*(volatile unsigned long*) 0xFFFFF860) /* (PIOC)
|
|
Pull-up Disable Register */
|
|
#define AT91C_PIOC_IFDR (*(volatile unsigned long*) 0xFFFFF824) /* (PIOC)
|
|
Input Filter Disable Register */
|
|
#define AT91C_PIOC_IER (*(volatile unsigned long*) 0xFFFFF840) /* (PIOC)
|
|
Interrupt Enable Register */
|
|
#define AT91C_PIOC_OSR (*(volatile unsigned long*) 0xFFFFF818) /* (PIOC)
|
|
Output Status Register */
|
|
#define AT91C_PIOC_ODSR (*(volatile unsigned long*) 0xFFFFF838) /* (PIOC)
|
|
Output Data Status Register */
|
|
#define AT91C_PIOC_ISR (*(volatile unsigned long*) 0xFFFFF84C) /* (PIOC)
|
|
Interrupt Status Register */
|
|
#define AT91C_PIOC_IFER (*(volatile unsigned long*) 0xFFFFF820) /* (PIOC)
|
|
Input Filter Enable Register */
|
|
|
|
/* Register definition for PMC peripheral */
|
|
#define AT91C_PMC_PCER (*(volatile unsigned long*) 0xFFFFFC10) /* (PMC)
|
|
Peripheral Clock Enable Register */
|
|
#define AT91C_PMC_PCKR (*(volatile unsigned long*) 0xFFFFFC40) /* (PMC)
|
|
Programmable Clock Register */
|
|
#define AT91C_PMC_MCKR (*(volatile unsigned long*) 0xFFFFFC30) /* (PMC)
|
|
Master Clock Register */
|
|
#define AT91C_PMC_PLLAR (*(volatile unsigned long*) 0xFFFFFC28) /* (PMC)
|
|
PLL A Register */
|
|
#define AT91C_PMC_PCDR (*(volatile unsigned long*) 0xFFFFFC14) /* (PMC)
|
|
Peripheral Clock Disable Register */
|
|
#define AT91C_PMC_SCSR (*(volatile unsigned long*) 0xFFFFFC08) /* (PMC)
|
|
System Clock Status Register */
|
|
#define AT91C_PMC_MCFR (*(volatile unsigned long*) 0xFFFFFC24) /* (PMC)
|
|
Main Clock Frequency Register */
|
|
#define AT91C_PMC_IMR (*(volatile unsigned long*) 0xFFFFFC6C) /* (PMC)
|
|
Interrupt Mask Register */
|
|
#define AT91C_PMC_IER (*(volatile unsigned long*) 0xFFFFFC60) /* (PMC)
|
|
Interrupt Enable Register */
|
|
#define AT91C_PMC_MOR (*(volatile unsigned long *) 0xFFFFFC20) /* (PMC)
|
|
Main Oscillator Register */
|
|
#define AT91C_PMC_IDR (*(volatile unsigned long *) 0xFFFFFC64) /* (PMC)
|
|
Interrupt Disable Register */
|
|
#define AT91C_PMC_PLLBR (*(volatile unsigned long*) 0xFFFFFC2C) /* (PMC)
|
|
PLL B Register */
|
|
#define AT91C_PMC_SCDR (*(volatile unsigned long*) 0xFFFFFC04) /* (PMC)
|
|
System Clock Disable Register */
|
|
#define AT91C_PMC_PCSR (*(volatile unsigned long*) 0xFFFFFC18) /* (PMC)
|
|
Peripheral Clock Status Register */
|
|
#define AT91C_PMC_SCER (*(volatile unsigned long*) 0xFFFFFC00) /* (PMC)
|
|
System Clock Enable Register */
|
|
#define AT91C_PMC_SR (*(volatile unsigned long*) 0xFFFFFC68) /* (PMC)
|
|
Status Register */
|
|
|
|
/* Register definition for PITC peripheral */
|
|
#define AT91C_PITC_PIVR (*(volatile unsigned long*) 0xFFFFFD38) /* (PITC)
|
|
Period Interval Value Register */
|
|
#define AT91C_PITC_PISR (*(volatile unsigned long*) 0xFFFFFD34) /* (PITC)
|
|
Period Interval Status Register */
|
|
#define AT91C_PITC_PIIR (*(volatile unsigned long*) 0xFFFFFD3C) /* (PITC)
|
|
Period Interval Image Register */
|
|
#define AT91C_PITC_PIMR (*(volatile unsigned long*) 0xFFFFFD30) /* (PITC)
|
|
Period Interval Mode Register */
|
|
|
|
/* PIO DEFINITIONS FOR AT91SAM9260 */
|
|
#define AT91C_PIO_PA0 (1 << 0) /* Pin Controlled by PA0 */
|
|
#define AT91C_PIO_PA1 (1 << 1) /* Pin Controlled by PA1 */
|
|
#define AT91C_PIO_PA10 (1 << 10) /* Pin Controlled by PA10 */
|
|
#define AT91C_PIO_PA11 (1 << 11) /* Pin Controlled by PA11 */
|
|
#define AT91C_PIO_PA12 (1 << 12) /* Pin Controlled by PA12 */
|
|
#define AT91C_PIO_PA13 (1 << 13) /* Pin Controlled by PA13 */
|
|
#define AT91C_PIO_PA14 (1 << 14) /* Pin Controlled by PA14 */
|
|
#define AT91C_PIO_PA15 (1 << 15) /* Pin Controlled by PA15 */
|
|
#define AT91C_PIO_PA16 (1 << 16) /* Pin Controlled by PA16 */
|
|
#define AT91C_PIO_PA17 (1 << 17) /* Pin Controlled by PA17 */
|
|
#define AT91C_PIO_PA18 (1 << 18) /* Pin Controlled by PA18 */
|
|
#define AT91C_PIO_PA19 (1 << 19) /* Pin Controlled by PA19 */
|
|
#define AT91C_PIO_PA2 (1 << 2) /* Pin Controlled by PA2 */
|
|
#define AT91C_PIO_PA20 (1 << 20) /* Pin Controlled by PA20 */
|
|
#define AT91C_PIO_PA21 (1 << 21) /* Pin Controlled by PA21 */
|
|
#define AT91C_PIO_PA22 (1 << 22) /* Pin Controlled by PA22 */
|
|
#define AT91C_PIO_PA23 (1 << 23) /* Pin Controlled by PA23 */
|
|
#define AT91C_PIO_PA24 (1 << 24) /* Pin Controlled by PA24 */
|
|
#define AT91C_PIO_PA25 (1 << 25) /* Pin Controlled by PA25 */
|
|
#define AT91C_PIO_PA26 (1 << 26) /* Pin Controlled by PA26 */
|
|
#define AT91C_PIO_PA27 (1 << 27) /* Pin Controlled by PA27 */
|
|
#define AT91C_PIO_PA28 (1 << 28) /* Pin Controlled by PA28 */
|
|
#define AT91C_PIO_PA29 (1 << 29) /* Pin Controlled by PA29 */
|
|
#define AT91C_PIO_PA3 (1 << 3) /* Pin Controlled by PA3 */
|
|
#define AT91C_PIO_PA30 (1 << 30) /* Pin Controlled by PA30 */
|
|
#define AT91C_PIO_PA31 (1 << 31) /* Pin Controlled by PA31 */
|
|
#define AT91C_PIO_PA4 (1 << 4) /* Pin Controlled by PA4 */
|
|
#define AT91C_PIO_PA5 (1 << 5) /* Pin Controlled by PA5 */
|
|
#define AT91C_PIO_PA6 (1 << 6) /* Pin Controlled by PA6 */
|
|
#define AT91C_PIO_PA7 (1 << 7) /* Pin Controlled by PA7 */
|
|
#define AT91C_PIO_PA8 (1 << 8) /* Pin Controlled by PA8 */
|
|
#define AT91C_PIO_PA9 (1 << 9) /* Pin Controlled by PA9 */
|
|
#define AT91C_PIO_PB0 (1 << 0) /* Pin Controlled by PB0 */
|
|
#define AT91C_PIO_PB1 (1 << 1) /* Pin Controlled by PB1 */
|
|
#define AT91C_PIO_PB10 (1 << 10) /* Pin Controlled by PB10 */
|
|
#define AT91C_PIO_PB11 (1 << 11) /* Pin Controlled by PB11 */
|
|
#define AT91C_PIO_PB12 (1 << 12) /* Pin Controlled by PB12 */
|
|
#define AT91C_PIO_PB13 (1 << 13) /* Pin Controlled by PB13 */
|
|
#define AT91C_PIO_PB14 (1 << 14) /* Pin Controlled by PB14 */
|
|
#define AT91C_PIO_PB15 (1 << 15) /* Pin Controlled by PB15 */
|
|
#define AT91C_PIO_PB16 (1 << 16) /* Pin Controlled by PB16 */
|
|
#define AT91C_PIO_PB17 (1 << 17) /* Pin Controlled by PB17 */
|
|
#define AT91C_PIO_PB18 (1 << 18) /* Pin Controlled by PB18 */
|
|
#define AT91C_PIO_PB19 (1 << 19) /* Pin Controlled by PB19 */
|
|
#define AT91C_PIO_PB2 (1 << 2) /* Pin Controlled by PB2 */
|
|
#define AT91C_PIO_PB20 (1 << 20) /* Pin Controlled by PB20 */
|
|
#define AT91C_PIO_PB21 (1 << 21) /* Pin Controlled by PB21 */
|
|
#define AT91C_PIO_PB22 (1 << 22) /* Pin Controlled by PB22 */
|
|
#define AT91C_PIO_PB23 (1 << 23) /* Pin Controlled by PB23 */
|
|
#define AT91C_PIO_PB24 (1 << 24) /* Pin Controlled by PB24 */
|
|
#define AT91C_PIO_PB25 (1 << 25) /* Pin Controlled by PB25 */
|
|
#define AT91C_PIO_PB26 (1 << 26) /* Pin Controlled by PB26 */
|
|
#define AT91C_PIO_PB27 (1 << 27) /* Pin Controlled by PB27 */
|
|
#define AT91C_PIO_PB28 (1 << 28) /* Pin Controlled by PB28 */
|
|
#define AT91C_PIO_PB29 (1 << 29) /* Pin Controlled by PB29 */
|
|
#define AT91C_PIO_PB3 (1 << 3) /* Pin Controlled by PB3 */
|
|
#define AT91C_PIO_PB30 (1 << 30) /* Pin Controlled by PB30 */
|
|
#define AT91C_PIO_PB31 (1 << 31) /* Pin Controlled by PB31 */
|
|
#define AT91C_PIO_PB4 (1 << 4) /* Pin Controlled by PB4 */
|
|
#define AT91C_PIO_PB5 (1 << 5) /* Pin Controlled by PB5 */
|
|
#define AT91C_PIO_PB6 (1 << 6) /* Pin Controlled by PB6 */
|
|
#define AT91C_PIO_PB7 (1 << 7) /* Pin Controlled by PB7 */
|
|
#define AT91C_PIO_PB8 (1 << 8) /* Pin Controlled by PB8 */
|
|
#define AT91C_PIO_PB9 (1 << 9) /* Pin Controlled by PB9 */
|
|
#define AT91C_PIO_PC0 (1 << 0) /* Pin Controlled by PC0 */
|
|
#define AT91C_PIO_PC1 (1 << 1) /* Pin Controlled by PC1 */
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#define AT91C_PIO_PC10 (1 << 10) /* Pin Controlled by PC10 */
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#define AT91C_PIO_PC11 (1 << 11) /* Pin Controlled by PC11 */
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#define AT91C_PIO_PC12 (1 << 12) /* Pin Controlled by PC12 */
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#define AT91C_PIO_PC13 (1 << 13) /* Pin Controlled by PC13 */
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#define AT91C_PIO_PC14 (1 << 14) /* Pin Controlled by PC14 */
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#define AT91C_PIO_PC15 (1 << 15) /* Pin Controlled by PC15 */
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#define AT91C_PIO_PC16 (1 << 16) /* Pin Controlled by PC16 */
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#define AT91C_PIO_PC17 (1 << 17) /* Pin Controlled by PC17 */
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#define AT91C_PIO_PC18 (1 << 18) /* Pin Controlled by PC18 */
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#define AT91C_PIO_PC19 (1 << 19) /* Pin Controlled by PC19 */
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#define AT91C_PIO_PC2 (1 << 2) /* Pin Controlled by PC2 */
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#define AT91C_PIO_PC20 (1 << 20) /* Pin Controlled by PC20 */
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#define AT91C_PIO_PC21 (1 << 21) /* Pin Controlled by PC21 */
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#define AT91C_PIO_PC22 (1 << 22) /* Pin Controlled by PC22 */
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#define AT91C_PIO_PC23 (1 << 23) /* Pin Controlled by PC23 */
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#define AT91C_PIO_PC24 (1 << 24) /* Pin Controlled by PC24 */
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#define AT91C_PIO_PC25 (1 << 25) /* Pin Controlled by PC25 */
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#define AT91C_PIO_PC26 (1 << 26) /* Pin Controlled by PC26 */
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#define AT91C_PIO_PC27 (1 << 27) /* Pin Controlled by PC27 */
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#define AT91C_PIO_PC28 (1 << 28) /* Pin Controlled by PC28 */
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#define AT91C_PIO_PC29 (1 << 29) /* Pin Controlled by PC29 */
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#define AT91C_PIO_PC3 (1 << 3) /* Pin Controlled by PC3 */
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#define AT91C_PIO_PC30 (1 << 30) /* Pin Controlled by PC30 */
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#define AT91C_PIO_PC31 (1 << 31) /* Pin Controlled by PC31 */
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#define AT91C_PIO_PC4 (1 << 4) /* Pin Controlled by PC4 */
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#define AT91C_PIO_PC5 (1 << 5) /* Pin Controlled by PC5 */
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#define AT91C_PIO_PC6 (1 << 6) /* Pin Controlled by PC6 */
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#define AT91C_PIO_PC7 (1 << 7) /* Pin Controlled by PC7 */
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#define AT91C_PIO_PC8 (1 << 8) /* Pin Controlled by PC8 */
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#define AT91C_PIO_PC9 (1 << 9) /* Pin Controlled by PC9 */
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/* PERIPHERAL ID DEFINITIONS FOR AT91SAM9260 */
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#define AT91C_ID_FIQ ( 0) /* Advanced Interrupt Controller (FIQ) */
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#define AT91C_ID_SYS ( 1) /* System Controller */
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#define AT91C_ID_PIOA ( 2) /* Parallel IO Controller A */
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#define AT91C_ID_PIOB ( 3) /* Parallel IO Controller B */
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#define AT91C_ID_PIOC ( 4) /* Parallel IO Controller C */
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#define AT91C_ID_ADC ( 5) /* ADC */
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#define AT91C_ID_US0 ( 6) /* USART 0 */
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#define AT91C_ID_US1 ( 7) /* USART 1 */
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#define AT91C_ID_US2 ( 8) /* USART 2 */
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#define AT91C_ID_MCI ( 9) /* Multimedia Card Interface 0 */
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#define AT91C_ID_UDP (10) /* USB Device Port */
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#define AT91C_ID_TWI (11) /* Two-Wire Interface */
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#define AT91C_ID_SPI0 (12) /* Serial Peripheral Interface 0 */
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#define AT91C_ID_SPI1 (13) /* Serial Peripheral Interface 1 */
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#define AT91C_ID_SSC0 (14) /* Serial Synchronous Controller 0 */
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#define AT91C_ID_TC0 (17) /* Timer Counter 0 */
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#define AT91C_ID_TC1 (18) /* Timer Counter 1 */
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#define AT91C_ID_TC2 (19) /* Timer Counter 2 */
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#define AT91C_ID_UHP (20) /* USB Host Port */
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#define AT91C_ID_EMAC (21) /* Ethernet Mac */
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#define AT91C_ID_HISI (22) /* Image Sensor Interface */
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#define AT91C_ID_US3 (23) /* USART 3 */
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#define AT91C_ID_US4 (24) /* USART 4 */
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#define AT91C_ID_US5 (25) /* USART 5 */
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#define AT91C_ID_TC3 (26) /* Timer Counter 3 */
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#define AT91C_ID_TC4 (27) /* Timer Counter 4 */
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#define AT91C_ID_TC5 (28) /* Timer Counter 5 */
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#define AT91C_ID_IRQ0 (29) /* Advanced Interrupt Controller (IRQ0) */
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#define AT91C_ID_IRQ1 (30) /* Advanced Interrupt Controller (IRQ1) */
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#define AT91C_ID_IRQ2 (31) /* Advanced Interrupt Controller (IRQ2) */
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#define AT91C_ALL_INT (0xFFFE7FFF) /* ALL VALID INTERRUPTS */
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/* MEMORY MAPPING DEFINITIONS FOR AT91SAM9260 */
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#define AT91C_IRAM_1 (0x00200000) /* Maximum IRAM_1 Area : 4Kbyte
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base address */
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#define AT91C_IRAM_1_SIZE (0x00001000) /* Maximum IRAM_1 Area : 4Kbyte size
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in byte (4 Kbytes) */
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#define AT91C_EBI_SDRAM_32BIT (0x20000000) /* SDRAM on EBI Chip Select 1
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base address */
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#define AT91C_BASE_AIC 0xFFFFF000 /* (AIC) Base Address */
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