8e07d68452
The JZ misc allows to enable and test SRAM.
The XBurst code uses the coprocessor interface to analyse the cpu. It also
provides a test platform for various features like EBASE and exceptions.
I was able to test and confirm that on jz4760b (thus xburst), EBASE works
(but top 2 bits are not controllable and always 01). The processor claims
to support vector interrupts but this is untested. The values in ConfigX
are not to be trusted blindly, clearly some are wrong. I tried to use the
JZ4780 Config7 "ebase gate" to change bit 30 of EBASE but it does not work,
which suggests that JZ480 uses a newer version of XBurst. Detailled log below:
> ./hwstub_shell -q -f lua/xburst.lua -e "XBURST.init()"
[...]
XBurst:
PRId: 0x2ed0024f
CPU: JZ4760(B)
Config: 0x80000483
Architecture Type: MIPS32
Architecture Level: Release 2 (or more)
MMU Type: Standard TLB
Config1: 0x3e63318a
MMU Size: 32
ICache
Sets per way: 128
Ways: 4
Line size: 32
DCache
Sets per way: 128
Ways: 4
Line size: 32
FPU: no
Config2: 0x80000000
Config3: 0x20
Vectored interrupt: yes
Config7: 0x0
> ./hwstub_shell -q -e 'require("jz/misc"); JZ.misc.enable_sram()' \
-f lua/xburst.lua -e "XBURST.test_ebase(0x80000000);XBURST.test_ebase(0xb32d0000)
[...]
Testing EBASE...
Disable BEV
SR value: 0x2000fc00
EBASE value: 0x80000000
Value after writing 0x80000000: 0x80000000
Value after writing 0x80040000: 0x80040000
Test result: EBase seems to work
Disable config7 gate: write 0x0 to Config7
Value after writing 0xfffff000: 0xbffff000
Enable config7 gate: write 0x80 to Config7
Value after writing 0xc0000000: 0x80000000
Config7 result: Config7 gate does not work
Exception test with EBASE at 0x80000000...
Writing instructions to memory
Old SR: 0x2000fc00
New SR: 0xfc00
EBASE: 80000000
Before: cafebabe
After: deadbeef
Exception result: Exception and EBASE are working
Testing EBASE...
Disable BEV
SR value: 0x2000fc00
EBASE value: 0x80000000
Value after writing 0x80000000: 0x80000000
Value after writing 0x80040000: 0x80040000
Test result: EBase seems to work
Disable config7 gate: write 0x0 to Config7
Value after writing 0xfffff000: 0xbffff000
Enable config7 gate: write 0x80 to Config7
Value after writing 0xc0000000: 0x80000000
Config7 result: Config7 gate does not work
Exception test with EBASE at 0xb32d0000...
Writing instructions to memory
Old SR: 0x2000fc00
New SR: 0xfc00
EBASE: b32d0000
Before: cafebabe
After: deadbeef
Exception result: Exception and EBASE are working
Change-Id: I894227981a141a8c14419b36ed9f519baf145ad1
43 lines
1.2 KiB
Lua
43 lines
1.2 KiB
Lua
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-- MISC --
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----------
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JZ.misc = {}
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function JZ.misc.enable_sram()
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HW.CPM.CLKGATE1.SRAM.clr()
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HW.CPM.CLKGATE1.AHB1.clr()
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end
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function JZ.misc.test_sram()
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DEV.write32(0xb32d0000, 0xaaaa5555)
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if DEV.read32(0xb32d0000) ~= 0xaaaa5555 then
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error("SRAM is not working")
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end
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DEV.write32(0xb32d0000, 0xdeadbeef)
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if DEV.read32(0xb32d0000) ~= 0xdeadbeef then
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error("SRAM is not working")
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end
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print("SRAM seems to be working")
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size = 0
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for i=4,64*1024,4 do
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DEV.write32(0xb32d0000, 0xdeadbeef)
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DEV.write32(0xb32d0000 + i, 0xcafebabe)
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if DEV.read32(0xb32d0000 + i) ~= 0xcafebabe or DEV.read32(0xb32d0000) == 0xcafebabe then
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size = i
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break
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end
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end
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print(string.format("SRAM size: 0x%x (%d KiB)", size, size / 1024))
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-- double check
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for i=0,size-1,2 do
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DEV.write16(0xb32d0000 + i, i)
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end
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for i=0,size-1,2 do
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if DEV.read16(0xb32d0000 + i) ~= i then
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error(string.format("SRAM size is not confirmed: read @%x gives %d instead of %d",
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0xb32d0000 + i, DEV.read16(0xb32d0000 + i), i))
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end
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end
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print("SRAM size confirmed and working")
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end
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