e682143af5
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18440 a1c6a512-1295-4272-9138-f99709370657
884 lines
23 KiB
C
884 lines
23 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 Rob Purchase
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "ata.h"
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#include "ata-nand-target.h"
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#include "system.h"
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#include <string.h>
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#include "led.h"
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#include "panic.h"
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#include "nand_id.h"
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/* The NAND driver is currently work-in-progress and as such contains
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some dead code and debug stuff, such as the next few lines. */
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#include "lcd.h"
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#include "font.h"
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#include "button.h"
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#include <sprintf.h>
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/* #define USE_TCC_LPT */
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/* #define USE_ECC_CORRECTION */
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/* for compatibility */
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int ata_spinup_time = 0;
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long last_disk_activity = -1;
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/** static, private data **/
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static bool initialized = false;
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static struct mutex ata_mtx SHAREDBSS_ATTR;
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#define SECTOR_SIZE 512
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#if defined(COWON_D2) || defined(IAUDIO_7)
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#define SEGMENT_ID_BIGENDIAN
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#define BLOCKS_PER_SEGMENT 4
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#else
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#define BLOCKS_PER_SEGMENT 1
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#endif
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/* NB: blocks_per_segment should become a runtime check based on NAND id */
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/* Segment type identifiers - main data area */
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#define SEGMENT_MAIN_LPT 0x12
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#define SEGMENT_MAIN_DATA1 0x13
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#define SEGMENT_MAIN_CACHE 0x15
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#define SEGMENT_MAIN_DATA2 0x17
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/* We don't touch the hidden area at all - these are for reference */
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#define SEGMENT_HIDDEN_LPT 0x22
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#define SEGMENT_HIDDEN_DATA1 0x23
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#define SEGMENT_HIDDEN_CACHE 0x25
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#define SEGMENT_HIDDEN_DATA2 0x27
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/* Offsets to spare area data */
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#define OFF_CACHE_PAGE_LOBYTE 2
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#define OFF_CACHE_PAGE_HIBYTE 3
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#define OFF_SEGMENT_TYPE 4
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#ifdef SEGMENT_ID_BIGENDIAN
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#define OFF_LOG_SEG_LOBYTE 7
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#define OFF_LOG_SEG_HIBYTE 6
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#else
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#define OFF_LOG_SEG_LOBYTE 6
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#define OFF_LOG_SEG_HIBYTE 7
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#endif
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/* Chip characteristics, initialised by nand_get_chip_info() */
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static int page_size = 0;
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static int spare_size = 0;
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static int pages_per_block = 0;
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static int blocks_per_bank = 0;
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static int pages_per_bank = 0;
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static int row_cycles = 0;
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static int col_cycles = 0;
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static int total_banks = 0;
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static int sectors_per_page = 0;
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static int bytes_per_segment = 0;
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static int sectors_per_segment = 0;
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static int segments_per_bank = 0;
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/* Maximum values for static buffers */
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#define MAX_PAGE_SIZE 4096
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#define MAX_SPARE_SIZE 128
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#define MAX_BLOCKS_PER_BANK 8192
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#define MAX_PAGES_PER_BLOCK 128
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#define MAX_BANKS 4
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#define MAX_SEGMENTS (MAX_BLOCKS_PER_BANK * MAX_BANKS / BLOCKS_PER_SEGMENT)
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/* Logical/Physical translation table */
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struct lpt_entry
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{
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short bank;
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short phys_segment;
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};
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static struct lpt_entry lpt_lookup[MAX_SEGMENTS];
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/* Write Caches */
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#define MAX_WRITE_CACHES 8
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struct write_cache
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{
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short bank;
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short phys_segment;
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short log_segment;
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short page_map[MAX_PAGES_PER_BLOCK * BLOCKS_PER_SEGMENT];
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};
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static struct write_cache write_caches[MAX_WRITE_CACHES];
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static int write_caches_in_use = 0;
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#ifdef USE_TCC_LPT
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/* Read buffer (used for reading LPT blocks only) */
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static unsigned char page_buf[MAX_PAGE_SIZE + MAX_SPARE_SIZE]
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__attribute__ ((aligned (4)));
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#endif
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#ifdef USE_ECC_CORRECTION
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static unsigned int ecc_sectors_corrected = 0;
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static unsigned int ecc_bits_corrected = 0;
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static unsigned int ecc_fail_count = 0;
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#endif
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/* Conversion functions */
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static inline int phys_segment_to_page_addr(int phys_segment, int page_in_seg)
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{
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#if BLOCKS_PER_SEGMENT == 4 /* D2 */
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int page_addr = phys_segment * pages_per_block * 2;
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if (page_in_seg & 1)
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{
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/* Data is located in block+1 */
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page_addr += pages_per_block;
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}
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if (page_in_seg & 2)
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{
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/* Data is located in second plane */
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page_addr += (blocks_per_bank/2) * pages_per_block;
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}
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page_addr += page_in_seg/4;
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#elif BLOCKS_PER_SEGMENT == 1 /* M200 */
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int page_addr = (phys_segment * pages_per_block) + page_in_seg;
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#endif
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return page_addr;
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}
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/* NAND physical access functions */
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static void nand_chip_select(int bank)
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{
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if (bank == -1)
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{
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/* Disable both chip selects */
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NAND_GPIO_CLEAR(CS_GPIO_BIT);
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NFC_CTRL |= NFC_CS0 | NFC_CS1;
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}
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else
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{
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/* NFC chip select */
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if (bank & 1)
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{
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NFC_CTRL &= ~NFC_CS0;
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NFC_CTRL |= NFC_CS1;
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}
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else
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{
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NFC_CTRL |= NFC_CS0;
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NFC_CTRL &= ~NFC_CS1;
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}
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/* Secondary chip select */
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if (bank & 2)
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NAND_GPIO_SET(CS_GPIO_BIT);
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else
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NAND_GPIO_CLEAR(CS_GPIO_BIT);
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}
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}
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static void nand_read_id(int bank, unsigned char* id_buf)
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{
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int i;
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/* Enable NFC bus clock */
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BCLKCTR |= DEV_NAND;
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/* Reset NAND controller */
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NFC_RST = 0;
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/* Set slow cycle timings since the chip is as yet unidentified */
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NFC_CTRL = (NFC_CTRL &~0xFFF) | 0x353;
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nand_chip_select(bank);
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/* Set write protect */
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NAND_GPIO_CLEAR(WE_GPIO_BIT);
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/* Reset command */
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NFC_CMD = 0xFF;
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/* Set 8-bit data width */
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NFC_CTRL &= ~NFC_16BIT;
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/* Read ID command, single address cycle */
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NFC_CMD = 0x90;
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NFC_SADDR = 0x00;
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/* Read the 5 chip ID bytes */
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for (i = 0; i < 5; i++)
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{
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id_buf[i] = NFC_SDATA & 0xFF;
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}
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nand_chip_select(-1);
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/* Disable NFC bus clock */
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BCLKCTR &= ~DEV_NAND;
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}
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static void nand_read_uid(int bank, unsigned int* uid_buf)
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{
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int i;
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/* Enable NFC bus clock */
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BCLKCTR |= DEV_NAND;
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/* Set cycle timing (stp = 1, pw = 3, hold = 1) */
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NFC_CTRL = (NFC_CTRL &~0xFFF) | 0x131;
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nand_chip_select(bank);
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/* Set write protect */
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NAND_GPIO_CLEAR(WE_GPIO_BIT);
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/* Set 8-bit data width */
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NFC_CTRL &= ~NFC_16BIT;
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/* Undocumented (SAMSUNG specific?) commands set the chip into a
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special mode allowing a normally-hidden UID block to be read. */
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NFC_CMD = 0x30;
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NFC_CMD = 0x65;
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/* Read command */
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NFC_CMD = 0x00;
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/* Write row/column address */
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for (i = 0; i < col_cycles; i++) NFC_SADDR = 0;
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for (i = 0; i < row_cycles; i++) NFC_SADDR = 0;
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/* End of read */
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NFC_CMD = 0x30;
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/* Wait until complete */
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while (!(NFC_CTRL & NFC_READY)) {};
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/* Copy data to buffer (data repeats after 8 words) */
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for (i = 0; i < 8; i++)
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{
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uid_buf[i] = NFC_WDATA;
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}
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/* Reset the chip back to normal mode */
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NFC_CMD = 0xFF;
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nand_chip_select(-1);
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/* Disable NFC bus clock */
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BCLKCTR &= ~DEV_NAND;
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}
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static void nand_read_raw(int bank, int row, int column, int size, void* buf)
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{
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int i;
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/* Enable NFC bus clock */
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BCLKCTR |= DEV_NAND;
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/* Set cycle timing (stp = 1, pw = 3, hold = 1) */
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NFC_CTRL = (NFC_CTRL &~0xFFF) | 0x131;
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nand_chip_select(bank);
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/* Set write protect */
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NAND_GPIO_CLEAR(WE_GPIO_BIT);
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/* Set 8-bit data width */
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NFC_CTRL &= ~NFC_16BIT;
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/* Read command */
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NFC_CMD = 0x00;
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/* Write column address */
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for (i = 0; i < col_cycles; i++)
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{
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NFC_SADDR = column & 0xFF;
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column = column >> 8;
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}
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/* Write row address */
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for (i = 0; i < row_cycles; i++)
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{
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NFC_SADDR = row & 0xFF;
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row = row >> 8;
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}
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/* End of read command */
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NFC_CMD = 0x30;
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/* Wait until complete */
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while (!(NFC_CTRL & NFC_READY)) {};
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/* Read data into page buffer */
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if (((unsigned int)buf & 3) || (size & 3))
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{
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/* Use byte copy since either the buffer or size are not word-aligned */
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/* TODO: Byte copy only where necessary (use words for mid-section) */
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for (i = 0; i < size; i++)
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{
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((unsigned char*)buf)[i] = NFC_SDATA;
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}
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}
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else
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{
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/* Use 4-byte copy as buffer and size are both word-aligned */
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for (i = 0; i < (size/4); i++)
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{
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((unsigned int*)buf)[i] = NFC_WDATA;
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}
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}
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nand_chip_select(-1);
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/* Disable NFC bus clock */
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BCLKCTR &= ~DEV_NAND;
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}
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static void nand_get_chip_info(void)
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{
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unsigned char manuf_id;
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unsigned char id_buf[8];
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/* Read chip id from bank 0 */
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nand_read_id(0, id_buf);
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manuf_id = id_buf[0];
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/* Identify the chip geometry */
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struct nand_info* nand_data = nand_identify(id_buf);
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if (nand_data == NULL)
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{
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panicf("Unknown NAND: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
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id_buf[0],id_buf[1],id_buf[2],id_buf[3],id_buf[4]);
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}
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page_size = nand_data->page_size;
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spare_size = nand_data->spare_size;
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pages_per_block = nand_data->pages_per_block;
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blocks_per_bank = nand_data->blocks_per_bank;
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col_cycles = nand_data->col_cycles;
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row_cycles = nand_data->row_cycles;
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pages_per_bank = blocks_per_bank * pages_per_block;
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segments_per_bank = blocks_per_bank / BLOCKS_PER_SEGMENT;
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bytes_per_segment = page_size * pages_per_block * BLOCKS_PER_SEGMENT;
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sectors_per_page = page_size / SECTOR_SIZE;
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sectors_per_segment = bytes_per_segment / SECTOR_SIZE;
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/* Establish how many banks are present */
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nand_read_id(1, id_buf);
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if (id_buf[0] == manuf_id)
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{
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/* Bank 1 is populated, now check if banks 2/3 are valid */
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nand_read_id(2, id_buf);
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if (id_buf[0] == manuf_id)
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{
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/* Bank 2 returned matching id - check if 2/3 are shadowing 0/1 */
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unsigned int uid_buf0[8];
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unsigned int uid_buf2[8];
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nand_read_uid(0, uid_buf0);
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nand_read_uid(2, uid_buf2);
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if (memcmp(uid_buf0, uid_buf2, 32) == 0)
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{
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/* UIDs match, assume banks 2/3 are shadowing 0/1 */
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total_banks = 2;
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}
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else
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{
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/* UIDs differ, assume banks 2/3 are valid */
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total_banks = 4;
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}
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}
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else
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{
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/* Bank 2 returned differing id - assume 2/3 are junk */
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total_banks = 2;
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}
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}
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else
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{
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/* Bank 1 returned differing id - assume it is junk */
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total_banks = 1;
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}
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/*
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Sanity checks:
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1. "BMP" tag at block 0, page 0, offset <page_size> [always present]
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2. On most D2s, <page_size>+3 is 'M' and <page_size>+4 is no. of banks.
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This is not present on some older players (formatted with early FW?)
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*/
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nand_read_raw(0, /* bank */
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0, /* page */
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page_size, /* offset */
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8, id_buf);
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if (strncmp(id_buf, "BMP", 3)) panicf("BMP tag not present");
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if (id_buf[3] == 'M')
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{
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if (id_buf[4] != total_banks) panicf("BMPM total_banks mismatch");
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}
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}
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static bool nand_read_sector_of_phys_page(int bank, int page,
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int sector, void* buf)
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{
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#ifndef USE_ECC_CORRECTION
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nand_read_raw(bank, page,
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sector * (SECTOR_SIZE+16),
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SECTOR_SIZE, buf);
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return true;
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#else
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/* Not yet implemented */
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return false;
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#endif
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}
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static bool nand_read_sector_of_phys_segment(int bank, int phys_segment,
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int page_in_seg, int sector,
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void* buf)
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{
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int page_addr = phys_segment_to_page_addr(phys_segment,
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page_in_seg);
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return nand_read_sector_of_phys_page(bank, page_addr, sector, buf);
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}
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static bool nand_read_sector_of_logical_segment(int log_segment, int sector,
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void* buf)
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{
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int page_in_segment = sector / sectors_per_page;
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int sector_in_page = sector % sectors_per_page;
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int bank = lpt_lookup[log_segment].bank;
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int phys_segment = lpt_lookup[log_segment].phys_segment;
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/* Check if any of the write caches refer to this segment/page.
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If present we need to read the cached page instead. */
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int cache_num = 0;
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bool found = false;
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while (!found && cache_num < write_caches_in_use)
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{
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if (write_caches[cache_num].log_segment == log_segment
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&& write_caches[cache_num].page_map[page_in_segment] != -1)
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{
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found = true;
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bank = write_caches[cache_num].bank;
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phys_segment = write_caches[cache_num].phys_segment;
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page_in_segment = write_caches[cache_num].page_map[page_in_segment];
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}
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else
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{
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cache_num++;
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}
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}
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return nand_read_sector_of_phys_segment(bank, phys_segment,
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page_in_segment,
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sector_in_page, buf);
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}
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/* Miscellaneous helper functions */
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static inline char get_segment_type(char* spare_buf)
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{
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return spare_buf[OFF_SEGMENT_TYPE];
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}
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static inline unsigned short get_log_segment_id(char* spare_buf)
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{
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return (spare_buf[OFF_LOG_SEG_HIBYTE] << 8) |
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spare_buf[OFF_LOG_SEG_LOBYTE];
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}
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static inline unsigned short get_cached_page_id(char* spare_buf)
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{
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return (spare_buf[OFF_CACHE_PAGE_HIBYTE] << 8) |
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spare_buf[OFF_CACHE_PAGE_LOBYTE];
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}
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#ifdef USE_TCC_LPT
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/* Reading the LPT from NAND is not yet fully understood. This code is therefore
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not enabled by default, as it gives much worse results than the bank-scanning
|
|
approach currently used.
|
|
|
|
The LPT is stored in a number of physical segments marked with type 0x12.
|
|
These are spread non-contiguously across the NAND, and are not stored in
|
|
sequential order.
|
|
|
|
The LPT data is stored in Sector 0 of the first <n> pages of each segment.
|
|
Each 32-bit value in sequence represents the physical location of a logical
|
|
segment. This is stored as (physical segment number * bank number).
|
|
|
|
NOTE: The bank numbers stored appear to be in reverse order to that required
|
|
by the nand_chip_select() function. The reason for this anomoly is unknown.
|
|
*/
|
|
|
|
static void read_lpt_block(int bank, int phys_segment)
|
|
{
|
|
int page = 1; /* table starts at page 1 of segment */
|
|
bool cont = true;
|
|
|
|
struct lpt_entry* lpt_ptr = NULL;
|
|
|
|
while (cont && page < pages_per_block)
|
|
{
|
|
int i = 0;
|
|
unsigned int* int_buf = (int*)page_buf;
|
|
|
|
nand_read_sector_of_phys_segment(bank, phys_segment,
|
|
page, 0, /* only sector 0 is used */
|
|
page_buf);
|
|
|
|
/* Find out which chunk of the LPT table this section contains.
|
|
Do this by reading the logical segment number of entry 0 */
|
|
if (lpt_ptr == NULL)
|
|
{
|
|
int first_bank = int_buf[0] / segments_per_bank;
|
|
int first_phys_segment = int_buf[0] % segments_per_bank;
|
|
|
|
/* Reverse the stored bank number */
|
|
if (total_banks > 1)
|
|
first_bank = (total_banks-1) - first_bank;
|
|
|
|
unsigned char spare_buf[16];
|
|
|
|
nand_read_raw(first_bank,
|
|
phys_segment_to_page_addr(first_phys_segment, 0),
|
|
SECTOR_SIZE, /* offset */
|
|
16, spare_buf);
|
|
|
|
int first_log_segment = get_log_segment_id(spare_buf);
|
|
|
|
lpt_ptr = &lpt_lookup[first_log_segment];
|
|
}
|
|
|
|
while (cont && (i < SECTOR_SIZE/4))
|
|
{
|
|
if (int_buf[i] != 0xFFFFFFFF)
|
|
{
|
|
int bank = int_buf[i] / segments_per_bank;
|
|
int phys_segment = int_buf[i] % segments_per_bank;
|
|
|
|
/* Reverse the stored bank number */
|
|
if (total_banks > 1)
|
|
bank = (total_banks-1) - bank;
|
|
|
|
lpt_ptr->bank = bank;
|
|
lpt_ptr->phys_segment = phys_segment;
|
|
|
|
lpt_ptr++;
|
|
i++;
|
|
}
|
|
else cont = false;
|
|
}
|
|
page++;
|
|
}
|
|
}
|
|
|
|
#endif /* USE_TCC_LPT */
|
|
|
|
|
|
static void read_write_cache_segment(int bank, int phys_segment)
|
|
{
|
|
int page;
|
|
unsigned char spare_buf[16];
|
|
|
|
if (write_caches_in_use == MAX_WRITE_CACHES)
|
|
panicf("Max NAND write caches reached");
|
|
|
|
write_caches[write_caches_in_use].bank = bank;
|
|
write_caches[write_caches_in_use].phys_segment = phys_segment;
|
|
|
|
/* Loop over each page in the phys segment (from page 1 onwards).
|
|
Read spare for 1st sector, store location of page in array. */
|
|
for (page = 1; page < pages_per_block * BLOCKS_PER_SEGMENT; page++)
|
|
{
|
|
unsigned short cached_page;
|
|
unsigned short log_segment;
|
|
|
|
nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, page),
|
|
SECTOR_SIZE, /* offset to first sector's spare */
|
|
16, spare_buf);
|
|
|
|
cached_page = get_cached_page_id(spare_buf);
|
|
log_segment = get_log_segment_id(spare_buf);
|
|
|
|
if (cached_page != 0xFFFF)
|
|
{
|
|
write_caches[write_caches_in_use].log_segment = log_segment;
|
|
write_caches[write_caches_in_use].page_map[cached_page] = page;
|
|
}
|
|
}
|
|
write_caches_in_use++;
|
|
}
|
|
|
|
|
|
int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int incount,
|
|
void* inbuf)
|
|
{
|
|
#ifdef HAVE_MULTIVOLUME
|
|
(void)drive; /* unused for now */
|
|
#endif
|
|
mutex_lock(&ata_mtx);
|
|
|
|
while (incount > 0)
|
|
{
|
|
int done = 0;
|
|
int segment = start / sectors_per_segment;
|
|
int secmod = start % sectors_per_segment;
|
|
|
|
while (incount > 0 && secmod < sectors_per_segment)
|
|
{
|
|
if (!nand_read_sector_of_logical_segment(segment, secmod, inbuf))
|
|
{
|
|
mutex_unlock(&ata_mtx);
|
|
return -1;
|
|
}
|
|
|
|
inbuf += SECTOR_SIZE;
|
|
incount--;
|
|
secmod++;
|
|
done++;
|
|
}
|
|
|
|
if (done < 0)
|
|
{
|
|
mutex_unlock(&ata_mtx);
|
|
return -1;
|
|
}
|
|
start += done;
|
|
}
|
|
|
|
mutex_unlock(&ata_mtx);
|
|
return 0;
|
|
}
|
|
|
|
int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count,
|
|
const void* outbuf)
|
|
{
|
|
#ifdef HAVE_MULTIVOLUME
|
|
(void)drive; /* unused for now */
|
|
#endif
|
|
|
|
/* TODO: Learn more about TNFTL and implement this one day... */
|
|
(void)start;
|
|
(void)count;
|
|
(void)outbuf;
|
|
return -1;
|
|
}
|
|
|
|
void ata_spindown(int seconds)
|
|
{
|
|
/* null */
|
|
(void)seconds;
|
|
}
|
|
|
|
bool ata_disk_is_active(void)
|
|
{
|
|
/* null */
|
|
return 0;
|
|
}
|
|
|
|
void ata_sleep(void)
|
|
{
|
|
/* null */
|
|
}
|
|
|
|
void ata_spin(void)
|
|
{
|
|
/* null */
|
|
}
|
|
|
|
/* Hardware reset protocol as specified in chapter 9.1, ATA spec draft v5 */
|
|
int ata_hard_reset(void)
|
|
{
|
|
/* null */
|
|
return 0;
|
|
}
|
|
|
|
int ata_soft_reset(void)
|
|
{
|
|
/* null */
|
|
return 0;
|
|
}
|
|
|
|
void ata_enable(bool on)
|
|
{
|
|
/* null - flash controller is enabled/disabled as needed. */
|
|
(void)on;
|
|
}
|
|
|
|
int ata_init(void)
|
|
{
|
|
int i, bank, phys_segment;
|
|
unsigned char spare_buf[16];
|
|
|
|
if (initialized) return 0;
|
|
|
|
#ifdef CPU_TCC77X
|
|
CSCFG2 = 0x318a8010;
|
|
|
|
GPIOC_FUNC &= ~(CS_GPIO_BIT | WE_GPIO_BIT);
|
|
GPIOC_FUNC |= 0x1;
|
|
#endif
|
|
|
|
/* Set GPIO direction for chip select & write protect */
|
|
NAND_GPIO_OUT_EN(CS_GPIO_BIT | WE_GPIO_BIT);
|
|
|
|
/* Get chip characteristics and number of banks */
|
|
nand_get_chip_info();
|
|
|
|
for (i = 0; i < MAX_SEGMENTS; i++)
|
|
{
|
|
lpt_lookup[i].bank = -1;
|
|
lpt_lookup[i].phys_segment = -1;
|
|
}
|
|
|
|
write_caches_in_use = 0;
|
|
|
|
for (i = 0; i < MAX_WRITE_CACHES; i++)
|
|
{
|
|
int page;
|
|
|
|
write_caches[i].log_segment = -1;
|
|
write_caches[i].bank = -1;
|
|
write_caches[i].phys_segment = -1;
|
|
|
|
for (page = 0; page < MAX_PAGES_PER_BLOCK * BLOCKS_PER_SEGMENT; page++)
|
|
{
|
|
write_caches[i].page_map[page] = -1;
|
|
}
|
|
}
|
|
|
|
/* Scan banks to build up block translation table */
|
|
for (bank = 0; bank < total_banks; bank++)
|
|
{
|
|
for (phys_segment = 0; phys_segment < segments_per_bank; phys_segment++)
|
|
{
|
|
/* Read spare bytes from first sector of each segment */
|
|
nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, 0),
|
|
SECTOR_SIZE, /* offset */
|
|
16, spare_buf);
|
|
|
|
switch (get_segment_type(spare_buf))
|
|
{
|
|
#ifdef USE_TCC_LPT
|
|
case SEGMENT_MAIN_LPT:
|
|
{
|
|
/* Log->Phys Translation table (for Main data area) */
|
|
read_lpt_block(bank, phys_segment);
|
|
break;
|
|
}
|
|
#else
|
|
case SEGMENT_MAIN_DATA2:
|
|
{
|
|
/* Main data area segment */
|
|
unsigned short log_segment = get_log_segment_id(spare_buf);
|
|
|
|
if (log_segment < MAX_SEGMENTS)
|
|
{
|
|
lpt_lookup[log_segment].bank = bank;
|
|
lpt_lookup[log_segment].phys_segment = phys_segment;
|
|
}
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
case SEGMENT_MAIN_CACHE:
|
|
{
|
|
/* Recently-written page data (for Main data area) */
|
|
read_write_cache_segment(bank, phys_segment);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifndef USE_TCC_LPT
|
|
/* Scan banks a second time as 0x13 segments appear to override 0x17 */
|
|
for (bank = 0; bank < total_banks; bank++)
|
|
{
|
|
for (phys_segment = 0; phys_segment < segments_per_bank; phys_segment++)
|
|
{
|
|
/* Read spare bytes from first sector of each segment */
|
|
nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, 0),
|
|
SECTOR_SIZE, /* offset */
|
|
16, spare_buf);
|
|
|
|
switch (get_segment_type(spare_buf)) /* block type */
|
|
{
|
|
case SEGMENT_MAIN_DATA1:
|
|
{
|
|
/* Main data area segment */
|
|
unsigned short log_segment = get_log_segment_id(spare_buf);
|
|
|
|
if (log_segment < MAX_SEGMENTS)
|
|
{
|
|
/* 0x13 seems to override 0x17, so store in our LPT */
|
|
lpt_lookup[log_segment].bank = bank;
|
|
lpt_lookup[log_segment].phys_segment = phys_segment;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
initialized = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* TEMP: This will return junk, it's here for compilation only */
|
|
unsigned short* ata_get_identify(void)
|
|
{
|
|
return (unsigned short*)0x21000000; /* Unused DRAM */
|
|
}
|