3482a55b83
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19741 a1c6a512-1295-4272-9138-f99709370657
209 lines
5.2 KiB
ArmAsm
209 lines
5.2 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .init.text,"ax",%progbits
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.global start
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start:
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/* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
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* loader
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*
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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*
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*/
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#if CONFIG_CPU == PP5002
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.equ PROC_ID, 0xc4000000
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.equ CPU_CTRL, 0xcf004054
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.equ CPU_STATUS, 0xcf004050
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.equ COP_CTRL, 0xcf004058
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.equ COP_STATUS, 0xcf004050
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.equ IIS_CONFIG, 0xc0002500
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.equ SLEEP, 0xca
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.equ WAKE, 0xce
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.equ CPUSLEEPING, 0x8000
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.equ COPSLEEPING, 0x4000
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.equ CACHE_CTRL, 0xcf004024
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.equ CACHE_ENAB, 0x2 /* Actually the CACHE_INIT flag */
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#else
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.equ PROC_ID, 0x60000000
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.equ CPU_CTRL, 0x60007000
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.equ CPU_STATUS, 0x60007000
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.equ COP_CTRL, 0x60007004
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.equ COP_STATUS, 0x60007004
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.equ IIS_CONFIG, 0x70002800
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.equ SLEEP, 0x80000000
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.equ WAKE, 0x0
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.equ CPUSLEEPING, 0x80000000
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.equ COPSLEEPING, 0x80000000
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.equ CACHE_CTRL, 0x6000c000
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.equ CACHE_ENAB, 0x1
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#endif
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
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#ifndef E200R_INSTALLER
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/* 1 - Copy the bootloader to IRAM */
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/* get the high part of our execute address */
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bic r0, pc, #0xff /* r4 = pc & 0xffffff00 */
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/* Copy bootloader to safe area - 0x40000000 (IRAM) */
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mov r1, #0x40000000
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ldr r2, =_dataend
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1:
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cmp r2, r1
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ldrhi r3, [r0], #4
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strhi r3, [r1], #4
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bhi 1b
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#ifndef IPOD_ARCH
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/* For builds on targets with mi4 firmware, scramble writes data to
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0xe0-0xeb, so jump past that. pad_skip must then exist at an
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address >= 0xec */
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b pad_skip
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.space 60*4
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pad_skip:
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#endif /* IPOD_ARCH */
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/* 2 - Jump both CPU and COP there */
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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#endif /* E200R_INSTALLER */
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start_loc:
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/* Find out which processor we are */
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ldr r0, =PROC_ID
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ldrb r0, [r0]
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cmp r0, #0x55
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beq cpu
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cop:
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/* put us (co-processor) to sleep */
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ldr r0, =COP_CTRL
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mov r1, #SLEEP
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str r1, [r0]
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nop
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nop
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/* Invalidate cache */
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mov r0, #1
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bl cache_op
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ldr r0, =startup_loc
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ldr pc, [r0]
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cpu:
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/* Wait for COP to be sleeping */
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ldr r0, =COP_STATUS
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1:
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ldr r1, [r0]
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tst r1, #COPSLEEPING
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beq 1b
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/* Initialise bss section to zero */
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ldr r0, =_edata
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ldr r1, =_end
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mov r2, #0
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1:
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cmp r1, r0
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strhi r2, [r0], #4
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bhi 1b
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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ldr r0, =stackbegin
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ldr r1, =0xdeadbeef
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1:
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cmp sp, r0
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strhi r1, [r0], #4
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bhi 1b
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/* execute the loader - this will load an image to 0x10000000 */
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bl main
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/* store actual startup location returned by main() */
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ldr r1, =startup_loc
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str r0, [r1]
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/* flush cache */
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mov r0, #0
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bl cache_op
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/* Wake up the coprocessor before executing the firmware */
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ldr r0, =COP_CTRL
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mov r1, #WAKE
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str r1, [r0]
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#if defined(SANSA_C200) || defined(PHILIPS_HDD1630)
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/* Magic for loading the c200 OF */
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ldr r0, =0xb00d10ad
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mov r1, #0x700
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ldr r2, =0xfff0
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mov r3, #0x7
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#endif
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ldr r4, =startup_loc
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ldr pc, [r4]
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startup_loc:
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.word 0x0
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#ifdef IPOD_ARCH
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.align 8 /* starts at 0x100 */
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.global boot_table
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boot_table:
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/* here comes the boot table, don't move its offset - preceding
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code+data must stay <= 256 bytes */
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.space 400
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#endif
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cache_op:
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ldr r2, =CACHE_CTRL
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ldr r1, [r2]
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tst r1, #CACHE_ENAB
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bxeq lr
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cmp r0, #0
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#ifdef CPU_PP502x
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ldr r0, =0xf000f044
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ldr r1, [r0]
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orrne r1, r1, #0x6
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orreq r1, r1, #0x2
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str r1, [r0]
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1:
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ldr r1, [r2]
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tst r1, #0x8000
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bne 1b
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#elif CONFIG_CPU == PP5002
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ldrne r0, =0xf0004000
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ldreq r0, =0xf000c000
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add r1, r0, #0x2000
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mov r2, #0
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1:
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cmp r1, r0
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strhi r2, [r0], #16
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bhi 1b
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#endif /* CPU type */
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bx lr
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