302 lines
10 KiB
ArmAsm
302 lines
10 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2010 by Karl Kurbjun
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#define CACHE_NONE 0
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#define CACHE_ALL 0x0C
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#define BUFFERED 0x04
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#define LONG_VECTORS 1
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/******************************************************************************
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* vectors: *
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* This is the ARM vector table *
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* Long call exception handlers are used for simplicity between flash *
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* bootloader and SDRAM main-application. These need to be copied to address *
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* 0x0 at start. *
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******************************************************************************/
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.section .vectors,"ax"
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.code 32
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.global _vectors
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@entry:
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_vectors:
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#if defined(SHORT_VECTORS) /* Use relative branch vectors (64 MB limit) */
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b _start /* Reset Vector */
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b undef_instr_handler /* Undefined instruction */
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b software_int_handler /* Software Vector */
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b prefetch_abort_handler /* Prefetch Abort */
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b data_abort_handler /* Data Abort */
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b reserved_handler /* Reserved/Unused */
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b irq_handler /* IRQ vector */
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b fiq_handler /* FIQ vector */
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#else
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#if defined(LONG_VECTORS)
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/* Load the PC with the word values stored below */
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ldr pc, [pc, #0x18] /* Reset */
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ldr pc, [pc, #0x18] /* Undefined instruction */
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ldr pc, [pc, #0x18] /* Software interrupt */
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ldr pc, [pc, #0x18] /* Prefetch Abort */
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ldr pc, [pc, #0x18] /* Data Abort */
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ldr pc, [pc, #0x18] /* Reserved/Unused */
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ldr pc, [pc, #0x18] /* IRQ */
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ldr pc, [pc, #0x18] /* FIQ */
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/* Addresses of the handlers */
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.word _start
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.word undef_instr_handler
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.word software_int_handler
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.word prefetch_abort_handler
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.word data_abort_handler
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.word reserved_handler
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.word irq_handler
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.word fiq_handler
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#else
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#error Vector type undefined
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#endif
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#endif
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/******************************************************************************
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* _start: *
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* This is the main entry point to the program *
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******************************************************************************/
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.section .init, "ax"
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.code 32
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.align 0x04
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.global _start
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_start:
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/* Go into supervisor state with IRQ's disabled.
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* This register is described in section "A2.5 Program status registers"
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* of the "ARM Architecture Reference Manual".
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*/
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msr cpsr, #0xd3
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/* Disable all the fancy stuff */
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mov r0, #0
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mcr p15, 0, r0, c1, c0, 0
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/* Disable data and instruction cache, high vectors (at 0xffff0000 instead
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* of 0x00000000)
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*/
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mrc p15, 0, r0, c1, c0, 0
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/* clear bits 13, 9:8 (--VI --RS) */
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bic r0, r0, #0x00003300
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/* clear bits 7, 2:0 (B--- -C-M) */
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bic r0, r0, #0x00000085
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/* make sure bit 2 (A) Align is set */
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orr r0, r0, #0x00000002
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mcr p15, 0, r0, c1, c0, 0
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/* Add a few cycles of delay before continuing due to system requirements */
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mov r0, #0x20
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bl _delay_cycles
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#if defined(BOOTLOADER) && !defined(CREATIVE_ZVx)
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bl _init_board
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#endif
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/* Copy exception handler code to address 0 */
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ldr r0, =_vectorscopy
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ldr r1, =_vectorsstart
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ldr r2, =_vectorsend
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bl _copy_section
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/* Add some delay time to make sure JTAG can be accessed cleanly */
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mov r0, #0x100000
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bl _delay_cycles
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#if defined(BOOTLOADER)
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/* Copy the DRAM */
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ldr r0, =_dramcopy
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ldr r1, =_dramstart
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ldr r2, =_dramend
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bl _copy_section
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#endif
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/* Zero out the IBSS */
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mov r0, #0
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ldr r1, =_ibss_start
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ldr r2, =_ibss_end
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bl _init_section
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/* Copy the IRAM */
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ldr r0, =_iramcopy
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ldr r1, =_iramstart
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ldr r2, =_iramend
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bl _copy_section
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/* Zero out the BSS */
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mov r0, #0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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bl _init_section
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/* Initialize fiq stack */
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ldr r0, =0xDEADBEEF
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ldr r1, =_fiq_stack_end /* Stack counts backwards, so end is first*/
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ldr r2, =_fiq_stack_start
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bl _init_section
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msr cpsr_c, #0xd1 /* Go into fiq state */
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ldr sp, =_fiq_stack_start /* set the fiq stack pointer */
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/* Initialize irq stack */
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ldr r0, =0xDEADBEEF /* Can be taken out; left for clarity */
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ldr r1, =_irq_stack_end /* Stack counts backwards, so end is first*/
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ldr r2, =_irq_stack_start
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bl _init_section
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msr cpsr_c, #0xd2 /* Go into irq state */
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ldr sp, =_irq_stack_start /* set the irq stack pointer */
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/* SVC, ABT, UNDEF share irq stack */
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msr cpsr_c, #0xd3 /* Go into svc state */
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ldr sp, =_irq_stack_start /* set svc stack pointer */
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msr cpsr_c, #0xd7 /* Go into abort state */
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ldr sp, =_irq_stack_start /* set the stack pointer */
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msr cpsr_c, #0xdb /* Go into undefined state */
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ldr sp, =_irq_stack_start /* set the stack pointer */
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/* Initialize program stack */
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msr cpsr_c, #0xdf /* Go into sys state */
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ldr r0, =0xDEADBEEF /* Can be taken out; left for clarity */
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ldr r1, =_pro_stack_end /* Stack counts backwards, so end is first*/
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ldr r2, =_pro_stack_start
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bl _init_section
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ldr sp, =_pro_stack_start /* set the sys stack pointer */
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/* MMU initialization */
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bl ttb_init
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/* Make sure everything is mapped on itself */
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ldr r0, =0x0
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ldr r1, =0x0
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ldr r2, =0x1000
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mov r3, #CACHE_NONE
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bl map_section
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/* Enable caching for FLASH */
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ldr r0, =_flash_start
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ldr r1, =_flash_start
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ldr r2, =_flash_sizem
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mov r3, #CACHE_ALL
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bl map_section
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/* Enable caching for RAM */
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ldr r0, =_sdram_start
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ldr r1, =_sdram_start
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ldr r2, =_sdram_sizem
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mov r3, #CACHE_ALL
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bl map_section
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bl enable_mmu
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/* Initial setup is complete, go into main */
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ldr pc, =main
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/* If main returns go into an infinite loop */
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b _dead_loop
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/* Constants go here (from _start - .ltorg): */
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.ltorg
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/******************************************************************************
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* _init_section: *
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* This function initializes a section with the 32-bit value specified. *
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******************************************************************************/
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.section .init, "ax"
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.code 32
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.align 0x04
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.global _init_section
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.type _init_section, %function
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/* r0 = init value
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* r1 = start location
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* r2 = end location
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*/
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/* This function will not run if end is less than or equal to start */
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_init_section:
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cmp r2, r1
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strhi r0, [r1], #4 /* store and increment start location */
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bhi _init_section
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bx lr
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.ltorg
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.size _init_section, .-_init_section
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/******************************************************************************
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* _copy_section: *
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* This function copies a section to a new location *
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******************************************************************************/
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.section .init, "ax"
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.code 32
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.align 0x04
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.global _copy_section
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.type _copy_section, %function
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/* r0 = source address
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* r1 = destination start address
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* r2 = destination end address
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*
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* r3 is a scratch register
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*/
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_copy_section:
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cmp r2, r1
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ldrhi r3, [r0], #4
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strhi r3, [r1], #4
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bhi _copy_section
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bx lr
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.ltorg
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.size _copy_section, .-_copy_section
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/******************************************************************************
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* _delay_cycles: *
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* This function delays for the specified number of cycles *
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******************************************************************************/
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.section .init, "ax"
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.code 32
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.align 0x04
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.global _delay_cycles
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.type _delay_cycles, %function
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/* r0 = number of cycles to delay */
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/* If r0 is zero it will be the maximum length delay */
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_delay_cycles:
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subs r0, r0, #1
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bne _delay_cycles
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bx lr
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.ltorg
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.size _delay_cycles, .-_delay_cycles
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/******************************************************************************
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* _dead_loop: Something really unexpected happened (like a reserved *
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* exception). Just hang. *
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******************************************************************************/
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_dead_loop:
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b _dead_loop
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.ltorg
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