434 lines
13 KiB
C
434 lines
13 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdio.h>
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#include "config.h"
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#include <lcd.h>
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#include "led.h"
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#include "system.h"
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#define default_interrupt(name,number) \
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extern __attribute__((weak,alias("UIE" #number))) void name (void); void UIE##number (void)
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#define reserve_interrupt(number) \
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void UIE##number (void)
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extern void reset_pc (void);
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extern void reset_sp (void);
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reserve_interrupt ( 0);
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reserve_interrupt ( 1);
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reserve_interrupt ( 2);
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reserve_interrupt ( 3);
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default_interrupt (GII, 4);
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reserve_interrupt ( 5);
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default_interrupt (ISI, 6);
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reserve_interrupt ( 7);
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reserve_interrupt ( 8);
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default_interrupt (CPUAE, 9);
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default_interrupt (DMAAE, 10);
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default_interrupt (NMI, 11);
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default_interrupt (UB, 12);
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reserve_interrupt ( 13);
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reserve_interrupt ( 14);
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reserve_interrupt ( 15);
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reserve_interrupt ( 16); // TCB #0
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reserve_interrupt ( 17); // TCB #1
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reserve_interrupt ( 18); // TCB #2
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reserve_interrupt ( 19); // TCB #3
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reserve_interrupt ( 20); // TCB #4
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reserve_interrupt ( 21); // TCB #5
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reserve_interrupt ( 22); // TCB #6
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reserve_interrupt ( 23); // TCB #7
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reserve_interrupt ( 24); // TCB #8
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reserve_interrupt ( 25); // TCB #9
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reserve_interrupt ( 26); // TCB #10
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reserve_interrupt ( 27); // TCB #11
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reserve_interrupt ( 28); // TCB #12
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reserve_interrupt ( 29); // TCB #13
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reserve_interrupt ( 30); // TCB #14
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reserve_interrupt ( 31); // TCB #15
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default_interrupt (TRAPA32, 32);
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default_interrupt (TRAPA33, 33);
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default_interrupt (TRAPA34, 34);
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default_interrupt (TRAPA35, 35);
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default_interrupt (TRAPA36, 36);
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default_interrupt (TRAPA37, 37);
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default_interrupt (TRAPA38, 38);
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default_interrupt (TRAPA39, 39);
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default_interrupt (TRAPA40, 40);
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default_interrupt (TRAPA41, 41);
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default_interrupt (TRAPA42, 42);
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default_interrupt (TRAPA43, 43);
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default_interrupt (TRAPA44, 44);
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default_interrupt (TRAPA45, 45);
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default_interrupt (TRAPA46, 46);
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default_interrupt (TRAPA47, 47);
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default_interrupt (TRAPA48, 48);
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default_interrupt (TRAPA49, 49);
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default_interrupt (TRAPA50, 50);
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default_interrupt (TRAPA51, 51);
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default_interrupt (TRAPA52, 52);
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default_interrupt (TRAPA53, 53);
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default_interrupt (TRAPA54, 54);
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default_interrupt (TRAPA55, 55);
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default_interrupt (TRAPA56, 56);
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default_interrupt (TRAPA57, 57);
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default_interrupt (TRAPA58, 58);
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default_interrupt (TRAPA59, 59);
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default_interrupt (TRAPA60, 60);
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default_interrupt (TRAPA61, 61);
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default_interrupt (TRAPA62, 62);
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default_interrupt (TRAPA63, 63);
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default_interrupt (IRQ0, 64);
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default_interrupt (IRQ1, 65);
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default_interrupt (IRQ2, 66);
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default_interrupt (IRQ3, 67);
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default_interrupt (IRQ4, 68);
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default_interrupt (IRQ5, 69);
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default_interrupt (IRQ6, 70);
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default_interrupt (IRQ7, 71);
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default_interrupt (DEI0, 72);
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reserve_interrupt ( 73);
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default_interrupt (DEI1, 74);
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reserve_interrupt ( 75);
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default_interrupt (DEI2, 76);
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reserve_interrupt ( 77);
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default_interrupt (DEI3, 78);
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reserve_interrupt ( 79);
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default_interrupt (IMIA0, 80);
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default_interrupt (IMIB0, 81);
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default_interrupt (OVI0, 82);
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reserve_interrupt ( 83);
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default_interrupt (IMIA1, 84);
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default_interrupt (IMIB1, 85);
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default_interrupt (OVI1, 86);
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reserve_interrupt ( 87);
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default_interrupt (IMIA2, 88);
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default_interrupt (IMIB2, 89);
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default_interrupt (OVI2, 90);
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reserve_interrupt ( 91);
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default_interrupt (IMIA3, 92);
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default_interrupt (IMIB3, 93);
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default_interrupt (OVI3, 94);
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reserve_interrupt ( 95);
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default_interrupt (IMIA4, 96);
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default_interrupt (IMIB4, 97);
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default_interrupt (OVI4, 98);
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reserve_interrupt ( 99);
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default_interrupt (REI0, 100);
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default_interrupt (RXI0, 101);
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default_interrupt (TXI0, 102);
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default_interrupt (TEI0, 103);
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default_interrupt (REI1, 104);
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default_interrupt (RXI1, 105);
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default_interrupt (TXI1, 106);
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default_interrupt (TEI1, 107);
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reserve_interrupt ( 108);
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default_interrupt (ADITI, 109);
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/* reset vectors are handled in crt0.S */
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void (*vbr[]) (void) __attribute__ ((section (".vectors"))) =
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{
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/*** 4 General Illegal Instruction ***/
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GII,
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/*** 5 Reserved ***/
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UIE5,
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/*** 6 Illegal Slot Instruction ***/
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ISI,
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/*** 7-8 Reserved ***/
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UIE7,UIE8,
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/*** 9 CPU Address Error ***/
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CPUAE,
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/*** 10 DMA Address Error ***/
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DMAAE,
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/*** 11 NMI ***/
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NMI,
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/*** 12 User Break ***/
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UB,
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/*** 13-31 Reserved ***/
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UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
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/*** 32-63 TRAPA #20...#3F ***/
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TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
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/*** 64-71 IRQ0-7 ***/
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IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
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/*** 72 DMAC0 ***/
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DEI0,
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/*** 73 Reserved ***/
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UIE73,
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/*** 74 DMAC1 ***/
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DEI1,
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/*** 75 Reserved ***/
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UIE75,
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/*** 76 DMAC2 ***/
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DEI2,
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/*** 77 Reserved ***/
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UIE77,
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/*** 78 DMAC3 ***/
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DEI3,
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/*** 79 Reserved ***/
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UIE79,
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/*** 80-82 ITU0 ***/
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IMIA0,IMIB0,OVI0,
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/*** 83 Reserved ***/
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UIE83,
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/*** 84-86 ITU1 ***/
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IMIA1,IMIB1,OVI1,
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/*** 87 Reserved ***/
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UIE87,
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/*** 88-90 ITU2 ***/
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IMIA2,IMIB2,OVI2,
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/*** 91 Reserved ***/
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UIE91,
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/*** 92-94 ITU3 ***/
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IMIA3,IMIB3,OVI3,
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/*** 95 Reserved ***/
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UIE95,
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/*** 96-98 ITU4 ***/
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IMIA4,IMIB4,OVI4,
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/*** 99 Reserved ***/
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UIE99,
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/*** 100-103 SCI0 ***/
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REI0,RXI0,TXI0,TEI0,
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/*** 104-107 SCI1 ***/
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REI1,RXI1,TXI1,TEI1,
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/*** 108 Parity Control Unit ***/
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UIE108,
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/*** 109 AD Converter ***/
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ADITI
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};
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void system_reboot (void)
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{
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cli ();
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asm volatile ("ldc\t%0,vbr" : : "r"(0));
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IPRA = 0;
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IPRB = 0;
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IPRC = 0;
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IPRD = 0;
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IPRE = 0;
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ICR = 0;
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asm volatile ("jmp @%0; mov.l @%1,r15" : :
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"r"(*(char*)0),"r"(4));
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}
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void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
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{
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bool state = true;
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unsigned int n;
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char str[32];
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asm volatile ("sts\tpr,%0" : "=r"(n));
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n = (n - (unsigned)UIE0 - 4)>>2; // get exception or interrupt number
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snprintf(str,sizeof(str),"** UIE%02x **",n);
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lcd_puts(0,0,str);
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snprintf(str,sizeof(str),"at %08x",pc);
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lcd_puts(0,1,str);
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while (1)
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{
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volatile int i;
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led (state);
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state = state?false:true;
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for (i = 0; i < 240000; ++i);
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}
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}
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asm (
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"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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|
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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|
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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|
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
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"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
|