f3cce72269
Now that we now that jz4760b implements EBASE, we can use it to rebase exceptions to use a k1seg address, that maps to the physical address of the TCSM0. It requires to enable HAB1 to have this translation. This most the most inefficient way to access tighly coupled memory ever, but it works. Change-Id: I894ca929c9835696102eb2fef44b06e6eaf96d44
68 lines
1.5 KiB
Text
68 lines
1.5 KiB
Text
#include "config.h"
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ENTRY(main)
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OUTPUT_ARCH(mips)
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STARTUP(jz4760b/crt0.o)
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MEMORY
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{
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/* see crt0.S from an an explanation of why TCSM0 is the best choice */
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TCSM0 : ORIGIN = TCSM0_ORIG, LENGTH = TCSM0_SIZE
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}
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SECTIONS
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{
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.itext :
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{
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relocstart = .;
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oc_codestart = .;
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*(.init.text*)
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*(.text*)
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*(.icode*)
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*(.data*)
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*(.rodata*)
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/* exceptions needs to be on a 0x1000 boundary */
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. = ALIGN(0x1000);
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tcsm0_irqbase = .;
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KEEP(*(.exception.tlb_refill))
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. = tcsm0_irqbase + 0x100;
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KEEP(*(.exception.cache_error))
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. = tcsm0_irqbase + 0x180;
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KEEP(*(.exception.general_exception))
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. = ALIGN(4);
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relocend = .;
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} > TCSM0
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/* tcsm0_irqbase is the address in the 0xf400xxxx address space, but for
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* EBASE, we want to the corresponding k1seg address, that maps to the
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* physical address of TCSM0 */
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irqbase = tcsm0_irqbase - TCSM0_ORIG + TCSM0_UNCACHED_ADDRESS;
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.bss (NOLOAD) :
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{
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bssbegin = .;
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*(.bss)
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. = ALIGN(4);
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bssend = .;
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} > TCSM0
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.stack (NOLOAD) :
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{
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oc_codeend = .;
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oc_stackstart = .;
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. += STACK_SIZE;
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oc_stackend = .;
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oc_bufferstart = .;
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} > TCSM0
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.ocend TCSM0_ORIG + TCSM0_SIZE (NOLOAD) :
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{
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oc_bufferend = .;
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} > TCSM0
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/DISCARD/ :
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{
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*(.note.*)
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*(.reginfo*)
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*(.MIPS*)
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}
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}
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