f9cc638efd
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7625 a1c6a512-1295-4272-9138-f99709370657
287 lines
8.2 KiB
C
287 lines
8.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Andy Young
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "lcd.h"
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#include "cpu.h"
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#include "kernel.h"
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#include "thread.h"
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#include "power.h"
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#include "debug.h"
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#include "system.h"
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#include "sprintf.h"
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#include "button.h"
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#include "string.h"
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#include "file.h"
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#include "buffer.h"
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#include "i2c-coldfire.h"
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#include "uda1380.h"
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/* ------------------------------------------------- */
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/* Local functions and variables */
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/* ------------------------------------------------- */
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int uda1380_write_reg(unsigned char reg, unsigned short value);
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unsigned short uda1380_regs[0x30];
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short uda1380_balance;
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short uda1380_volume;
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/* Definition of a playback configuration to start with */
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#define NUM_DEFAULT_REGS 13
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unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
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{
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REG_0, EN_DAC | EN_INT | EN_DEC | SYSCLK_256FS | WSPLL_25_50,
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REG_I2S, I2S_IFMT_IIS,
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REG_PWR, PON_PLL | PON_BIAS, /* PON_HP & PON_DAC is enabled later */
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REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f), /* 00=max, 3f=mute */
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REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20), /* 00=max, ff=mute */
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REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff), /* 00=max, ff=mute */
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REG_EQ, EQ_MODE_MAX, /* Bass and tremble = 0 dB */
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REG_MUTE, MUTE_MASTER | MUTE_CH2, /* Mute everything to start with */
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REG_MIX_CTL, MIX_CTL_MIX, /* Enable mixer */
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REG_DEC_VOL, 0,
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REG_PGA, MUTE_ADC,
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REG_ADC, SKIP_DCFIL,
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REG_AGC, 0
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};
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/* Returns 0 if register was written or -1 if write failed */
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int uda1380_write_reg(unsigned char reg, unsigned short value)
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{
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unsigned char data[4];
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data[0] = UDA1380_ADDR;
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data[1] = reg;
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data[2] = value >> 8;
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data[3] = value & 0xff;
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if (i2c_write(1, data, 4) != 4)
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{
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DEBUGF("uda1380 error reg=0x%x", reg);
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return -1;
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}
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uda1380_regs[reg] = value;
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return 0;
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}
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/**
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* Sets left and right master volume (0(max) to 252(muted))
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*/
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int uda1380_set_master_vol(int vol_l, int vol_r)
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{
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return uda1380_write_reg(REG_MASTER_VOL,
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MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
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}
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/**
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* Sets mixer volume for both channels (0(max) to 228(muted))
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*/
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int uda1380_set_mixer_vol(int channel1, int channel2)
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{
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return uda1380_write_reg(REG_MIX_VOL,
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MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2));
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}
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/**
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* Sets the bass value (0-12)
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*/
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void uda1380_set_bass(int value)
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{
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uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK) | BASSL(value) | BASSR(value));
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}
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/**
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* Sets the treble value (0-3)
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*/
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void uda1380_set_treble(int value)
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{
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uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK) | TREBLEL(value) | TREBLER(value));
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}
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/**
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* Mute (mute=1) or enable sound (mute=0)
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*
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*/
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int uda1380_mute(int mute)
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{
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unsigned int value = uda1380_regs[REG_MUTE];
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if (mute)
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value = value | MUTE_MASTER;
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else
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value = value & ~MUTE_MASTER;
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return uda1380_write_reg(REG_MUTE, value);
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}
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/* Returns 0 if successful or -1 if some register failed */
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int uda1380_set_regs(void)
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{
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int i;
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memset(uda1380_regs, 0, sizeof(uda1380_regs));
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/* Initialize all registers */
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for (i=0; i<NUM_DEFAULT_REGS; i++)
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{
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unsigned char reg = uda1380_defaults[i*2+0];
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unsigned short value = uda1380_defaults[i*2+1];
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if (uda1380_write_reg(reg, value) == -1)
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return -1;
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}
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return 0;
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}
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/* Silently enable / disable audio output */
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void uda1380_enable_output(bool enable)
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{
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if (enable) {
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP);
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} else {
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uda1380_write_reg(REG_MUTE, MUTE_MASTER);
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~PON_DAC);
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}
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}
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void uda1380_reset(void)
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{
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/* RESET signal */
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or_l(1<<29, &GPIO_OUT);
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or_l(1<<29, &GPIO_ENABLE);
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or_l(1<<29, &GPIO_FUNCTION);
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sleep(HZ/100);
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and_l(~(1<<29), &GPIO_OUT);
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}
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/* Initialize UDA1380 codec with default register values (uda1380_defaults) */
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int uda1380_init(void)
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{
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uda1380_reset();
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if (uda1380_set_regs() == -1)
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return -1;
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uda1380_balance = 0;
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uda1380_volume = 0x20; /* Taken from uda1380_defaults */
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return 0;
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}
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/* Nice shutdown of UDA1380 codec */
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void uda1380_close(void)
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{
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/* First enable mute and sleep a while */
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uda1380_write_reg(REG_MUTE, MUTE_MASTER);
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sleep(HZ/8);
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/* Then power off the rest of the chip */
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uda1380_write_reg(REG_PWR, 0);
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uda1380_write_reg(REG_0, 0); /* Disable codec */
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}
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/**
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* Calling this function enables the UDA1380 to send
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* sound samples over the I2S bus, which is connected
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* to the processor's IIS1 interface.
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*
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* source_mic: true=record from microphone, false=record from line-in
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*/
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void uda1380_enable_recording(bool source_mic)
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{
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uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
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if (source_mic)
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{
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL);
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uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK) | SEL_LNA | SEL_MIC | EN_DCFIL); /* VGA_GAIN: 0=0 dB, F=30dB */
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uda1380_write_reg(REG_PGA, 0);
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} else
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{
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL | PON_PGAR | PON_ADCR);
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uda1380_write_reg(REG_ADC, EN_DCFIL);
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uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA] & PGA_GAIN_MASK) | PGA_GAINL(0) | PGA_GAINR(0)); /* PGA_GAIN: 0=0 dB, F=24dB */
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}
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sleep(HZ/8);
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uda1380_write_reg(REG_I2S, uda1380_regs[REG_I2S] | I2S_MODE_MASTER);
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uda1380_write_reg(REG_MIX_CTL, MIX_MODE(1));
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}
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/**
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* Stop sending samples on the I2S bus
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*/
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void uda1380_disable_recording(void)
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{
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uda1380_write_reg(REG_PGA, MUTE_ADC);
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sleep(HZ/8);
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uda1380_write_reg(REG_I2S, I2S_IFMT_IIS);
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~(PON_LNA | PON_ADCL | PON_ADCR | PON_PGAL | PON_PGAR));
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uda1380_write_reg(REG_0, uda1380_regs[REG_0] & ~EN_ADC);
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uda1380_write_reg(REG_ADC, SKIP_DCFIL);
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}
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/**
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* Set recording gain and volume
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*
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* mic_gain : range 0 .. 15 -> 0 .. 30 dB gain
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* linein_gain : range 0 .. 15 -> 0 .. 24 dB gain
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*
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* adc_volume : range -127 .. 48 -> -63 .. 24 dB gain
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* note that 0 -> 0 dB gain..
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*/
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void uda1380_set_recvol(int mic_gain, int linein_gain, int adc_volume)
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{
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uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(adc_volume) | DEC_VOLR(adc_volume));
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uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA] & ~PGA_GAIN_MASK) | PGA_GAINL(linein_gain) | PGA_GAINR(linein_gain));
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uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & ~VGA_GAIN_MASK) | VGA_GAIN(mic_gain));
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}
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/**
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* Enable or disable recording monitor (so one can listen to the recording)
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*
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*/
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void uda1380_set_monitor(int enable)
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{
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if (enable) /* enable channel 2 */
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uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] & ~MUTE_CH2);
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else /* mute channel 2 */
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uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] | MUTE_CH2);
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}
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/* Change the order of the noise chaper, 5th order is recommended above 32kHz */
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void uda1380_set_nsorder(int order)
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{
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switch(order)
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{
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case 5:
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uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] | MIX_CTL_SEL_NS);
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break;
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case 3:
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default:
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uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] & ~MIX_CTL_SEL_NS);
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}
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}
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