187 lines
8 KiB
C
187 lines
8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
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* and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SSP_IMX233_H__
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#define __SSP_IMX233_H__
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#include "cpu.h"
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#include "system.h"
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#include "system-target.h"
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#include "pinctrl-imx233.h"
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#include "dma-imx233.h"
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/* ssp can value 1 or 2 */
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#define __SSP_SELECT(ssp, ssp1, ssp2) ((ssp) == 1 ? (ssp1) : (ssp2))
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#define INT_SRC_SSP_DMA(ssp) __SSP_SELECT(ssp, INT_SRC_SSP1_DMA, INT_SRC_SSP2_DMA)
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#define INT_SRC_SSP_ERROR(ssp) __SSP_SELECT(ssp, INT_SRC_SSP1_ERROR, INT_SRC_SSP2_ERROR)
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#define HW_SSP1_BASE 0x80010000
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#define HW_SSP2_BASE 0x80034000
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#define HW_SSP_BASE(ssp) __SSP_SELECT(ssp, HW_SSP1_BASE, HW_SSP2_BASE)
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#define HW_SSP_CTRL0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x0))
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#define HW_SSP_CTRL0__RUN (1 << 29)
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#define HW_SSP_CTRL0__SDIO_IRQ_CHECK (1 << 28)
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#define HW_SSP_CTRL0__LOCK_CS (1 << 27)
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#define HW_SSP_CTRL0__IGNORE_CRC (1 << 26)
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#define HW_SSP_CTRL0__READ (1 << 25)
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#define HW_SSP_CTRL0__DATA_XFER (1 << 24)
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#define HW_SSP_CTRL0__BUS_WIDTH_BM (3 << 22)
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#define HW_SSP_CTRL0__BUS_WIDTH_BP 22
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#define HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT 0
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#define HW_SSP_CTRL0__BUS_WIDTH__FOUR_BIT 1
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#define HW_SSP_CTRL0__BUS_WIDTH__EIGHT_BIT 2
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#define HW_SSP_CTRL0__WAIT_FOR_IRQ (1 << 21)
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#define HW_SSP_CTRL0__WAIT_FOR_CMD (1 << 20)
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#define HW_SSP_CTRL0__LONG_RESP (1 << 19)
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#define HW_SSP_CTRL0__CHECK_RESP (1 << 18)
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#define HW_SSP_CTRL0__GET_RESP (1 << 17)
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#define HW_SSP_CTRL0__ENABLE (1 << 16)
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#define HW_SSP_CTRL0__XFER_COUNT_BM 0xffff
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#define HW_SSP_CMD0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x10))
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#define HW_SSP_CMD0__SLOW_CLKING_EN (1 << 22)
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#define HW_SSP_CMD0__CONT_CLKING_EN (1 << 21)
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#define HW_SSP_CMD0__APPEND_8CYC (1 << 20)
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#define HW_SSP_CMD0__BLOCK_SIZE_BM (0xf << 16)
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#define HW_SSP_CMD0__BLOCK_SIZE_BP 16
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#define HW_SSP_CMD0__BLOCK_COUNT_BM (0xff << 8)
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#define HW_SSP_CMD0__BLOCK_COUNT_BP 8
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#define HW_SSP_CMD0__CMD_BM 0xff
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#define HW_SSP_CMD1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x20))
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#define HW_SSP_TIMING(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x50))
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#define HW_SSP_TIMING__CLOCK_TIMEOUT_BM 0xffff0000
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#define HW_SSP_TIMING__CLOCK_TIMEOUT_BP 16
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#define HW_SSP_TIMING__CLOCK_DIVIDE_BM 0xff00
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#define HW_SSP_TIMING__CLOCK_DIVIDE_BP 8
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#define HW_SSP_TIMING__CLOCK_RATE_BM 0xff
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#define HW_SSP_CTRL1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x60))
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#define HW_SSP_CTRL1__SDIO_IRQ (1 << 31)
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#define HW_SSP_CTRL1__SDIO_IRQ_EN (1 << 30)
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#define HW_SSP_CTRL1__RESP_ERR_IRQ (1 << 29)
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#define HW_SSP_CTRL1__RESP_ERR_IRQ_EN (1 << 28)
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#define HW_SSP_CTRL1__RESP_TIMEOUT_IRQ (1 << 27)
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#define HW_SSP_CTRL1__RESP_TIMEOUT_IRQ_EN (1 << 26)
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#define HW_SSP_CTRL1__DATA_TIMEOUT_IRQ (1 << 25)
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#define HW_SSP_CTRL1__DATA_TIMEOUT_IRQ_EN (1 << 24)
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#define HW_SSP_CTRL1__DATA_CRC_IRQ (1 << 23)
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#define HW_SSP_CTRL1__DATA_CRC_IRQ_EN (1 << 22)
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#define HW_SSP_CTRL1__FIFO_UNDERRUN_IRQ (1 << 21)
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#define HW_SSP_CTRL1__FIFO_UNDERRUN_IRQ_EN (1 << 20)
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#define HW_SSP_CTRL1__RECV_TIMEOUT_IRQ (1 << 17)
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#define HW_SSP_CTRL1__RECV_TIMEOUT_IRQ_EN (1 << 16)
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#define HW_SSP_CTRL1__FIFO_OVERRUN_IRQ (1 << 15)
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#define HW_SSP_CTRL1__FIFO_OVERRUN_IRQ_EN (1 << 14)
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#define HW_SSP_CTRL1__DMA_ENABLE (1 << 13)
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#define HW_SSP_CTRL1__SLAVE_OUT_DISABLE (1 << 11)
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#define HW_SSP_CTRL1__PHASE (1 << 10)
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#define HW_SSP_CTRL1__POLARITY (1 << 9)
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#define HW_SSP_CTRL1__SLAVE_MODE (1 << 8)
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#define HW_SSP_CTRL1__WORD_LENGTH_BM (0xf << 4)
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#define HW_SSP_CTRL1__WORD_LENGTH_BP 4
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#define HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS 0x7
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#define HW_SSP_CTRL1__SSP_MODE_BM 0xf
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#define HW_SSP_CTRL1__SSP_MODE__SD_MMC 0x3
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#define HW_SSP_CTRL1__ALL_IRQ 0xaaa28000
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#define HW_SSP_DATA(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x70))
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#define HW_SSP_SDRESP0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x80))
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#define HW_SSP_SDRESP1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x90))
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#define HW_SSP_SDRESP2(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xA0))
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#define HW_SSP_SDRESP3(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xB0))
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#define HW_SSP_STATUS(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xC0))
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#define HW_SSP_STATUS__RECV_TIMEOUT_STAT (1 << 11)
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#define HW_SSP_STATUS__TIMEOUT (1 << 12)
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#define HW_SSP_STATUS__DATA_CRC_ERR (1 << 13)
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#define HW_SSP_STATUS__RESP_TIMEOUT (1 << 14)
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#define HW_SSP_STATUS__RESP_ERR (1 << 15)
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#define HW_SSP_STATUS__RESP_CRC_ERR (1 << 16)
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#define HW_SSP_STATUS__CARD_DETECT (1 << 28)
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#define HW_SSP_STATUS__ALL_ERRORS 0x1f800
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#define HW_SSP_DEBUG(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x100))
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#define HW_SSP_VERSION(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x110))
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#define IMX233_MAX_SSP_XFER_SIZE IMX233_MAX_SINGLE_DMA_XFER_SIZE
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enum imx233_ssp_error_t
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{
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SSP_SUCCESS = 0,
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SSP_ERROR = -1,
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SSP_TIMEOUT = -2,
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};
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enum imx233_ssp_resp_t
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{
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SSP_NO_RESP = 0,
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SSP_SHORT_RESP,
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SSP_LONG_RESP
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};
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typedef void (*ssp_detect_cb_t)(int ssp);
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void imx233_ssp_init(void);
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void imx233_ssp_start(int ssp);
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void imx233_ssp_stop(int ssp);
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/* only softreset between start and stop or it might hang ! */
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void imx233_ssp_softreset(int ssp);
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void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout);
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void imx233_ssp_set_mode(int ssp, unsigned mode);
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void imx233_ssp_set_bus_width(int ssp, unsigned width);
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/* block_size uses the SSP format so it's actually the log_2 of the block_size */
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void imx233_ssp_set_block_size(int ssp, unsigned log_block_size);
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/* SD/MMC facilities */
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enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
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uint32_t cmd_arg, enum imx233_ssp_resp_t resp, void *buffer, unsigned block_count,
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bool wait4irq, bool read, uint32_t *resp_ptr);
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void imx233_ssp_setup_ssp1_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
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unsigned drive_strength, bool use_alt);
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void imx233_ssp_setup_ssp2_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
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unsigned drive_strength);
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/* after callback is fired, imx233_ssp_sdmmc_setup_detect needs to be called
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* to enable detection again. If first_time is true, the callback will
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* be called if the sd card is inserted when the function is called, otherwise
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* it will be called on the next insertion change.
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* By default, sd_detect=1 means sd inserted; invert reverses this behaviour */
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void imx233_ssp_sdmmc_setup_detect(int ssp, bool enable, ssp_detect_cb_t fn,
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bool first_time, bool invert);
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/* needs prior setup with imx233_ssp_sdmmc_setup_detect */
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bool imx233_ssp_sdmmc_is_detect_inverted(int spp);
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/* raw value of the detect pin */
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bool imx233_ssp_sdmmc_detect_raw(int ssp);
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/* corrected value given the invert setting */
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bool imx233_ssp_sdmmc_detect(int ssp);
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/* SD/MMC requires that the card be provided the clock during an init sequence of
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* at least 1msec (or 74 clocks). Does NOT touch the clock so it has to be correct. */
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void imx233_ssp_sd_mmc_power_up_sequence(int ssp);
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#endif /* __SSP_IMX233_H__ */
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