42774d3128
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24712 a1c6a512-1295-4272-9138-f99709370657
342 lines
12 KiB
C
342 lines
12 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: $
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*
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* Copyright (C) 2010 Dave Hooper
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*
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* ARM optimisations for ffmpeg's fft (used in fft-ffmpeg.c)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifdef CPU_ARM
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/* Start off with optimised variants of the butterflies that work
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nicely on arm */
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/* 1. where y and a share the same variable/register */
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#define BF_OPT(x,y,a,b) {\
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y = a + b;\
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x = y - (b<<1);\
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}
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/* 2. where y and b share the same variable/register */
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#define BF_OPT2(x,y,a,b) {\
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x = a - b;\
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y = x + (b<<1);\
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}
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/* 3. where y and b share the same variable/register (but y=(-b)) */
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#define BF_OPT2_REV(x,y,a,b) {\
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x = a + b;\
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y = x - (b<<1);\
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}
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/* standard BUTTERFLIES package. Note, we actually manually inline this
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in all the TRANSFORM macros below anyway */
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#define FFT_FFMPEG_INCL_OPTIMISED_BUTTERFLIES
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#define BUTTERFLIES(a0,a1,a2,a3) {\
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{\
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BF_OPT(t1, t5, t5, t1);\
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BF_OPT(t6, t2, t2, t6);\
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BF_OPT(a2.re, a0.re, a0.re, t5);\
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BF_OPT(a2.im, a0.im, a0.im, t2);\
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BF_OPT(a3.re, a1.re, a1.re, t6);\
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BF_OPT(a3.im, a1.im, a1.im, t1);\
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}\
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}
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#define FFT_FFMPEG_INCL_OPTIMISED_TRANSFORM
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/* on ARM, all the TRANSFORM_etc inlines use the following registers:
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r5,r6,r7,r8,r9,r10,r4,r12
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inputs are: z, n, STEP
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NOTE THAT THESE MACROS ACTUALLY CHANGE z INPUT INPLACE-
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so sequential actions, z += n*3, z -= n*2 etc etc matter
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*/
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#define TRANSFORM_POST_STORE( z, n ) {\
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/*{*/\
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/* BF_OPT(t1, t5, t5, t1);*/\
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/* BF_OPT(t6, t2, t2, t6);*/\
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/* BF_OPT(a2.re, a0.re, a0.re, t5);*/\
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/* BF_OPT(a2.im, a0.im, a0.im, t2);*/\
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/* BF_OPT(a3.re, a1.re, a1.re, t6);*/\
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/* BF_OPT(a3.im, a1.im, a1.im, t1);*/\
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/*}*/\
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z -= n*3;\
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/* r_re = my_z[0]; r_im = my_z[1]; */\
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{\
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register FFTSample rt0temp asm("r4");\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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BF_OPT(rt0temp, r_re, r_re, t5);\
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BF_OPT(t2, r_im, r_im, t2);\
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/* my_z[0] = r_re; my_z[1] = r_im; */\
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asm volatile( "stmia %[my_z], {%[r_re],%[r_im]}\n\t"::[my_z] "r" (z), [r_re] "r" (r_re), [r_im] "r" (r_im));\
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z += n;\
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/* r_re = my_z[0]; r_im = my_z[1]; */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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BF_OPT(t5, r_re, r_re, t6);\
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BF_OPT(t6, r_im, r_im, t1);\
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/* my_z[0] = r_re; my_z[1] = r_im; */\
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asm volatile( "stmia %[my_z], {%[r_re],%[r_im]}\n\t"::[my_z] "r" (z), [r_re] "r" (r_re), [r_im] "r" (r_im));\
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z += n;\
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/* my_z[0] = rt0temp; my_z[1] = t2; */\
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asm volatile( "stmia %[my_z], {%[rt0temp],%[t2]}\n\t"::[my_z] "r" (z), [rt0temp] "r" (rt0temp), [t2] "r" (t2));\
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z += n;\
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}\
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/* my_z[0] = t5; my_z[1] = t6; */\
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asm volatile( "stmia %[my_z], {%[t5],%[t6]}\n\t"::[my_z] "r" (z), [t5] "r" (t5), [t6] "r" (t6));\
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z -= n*3;\
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}
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#define TRANSFORM( z, n, wre_arg, wim_arg )\
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{\
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FFTSample wre = wre_arg, wim = wim_arg;\
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register FFTSample t1 asm("r5"),t2 asm("r6"),t5 asm("r7"),t6 asm("r8"),r_re asm("r9"),r_im asm("r10");\
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z += n*2; /* z[o2] */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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XPROD31_R(r_re, r_im, wre, wim, t1,t2);\
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\
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z += n; /* z[o3] */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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XNPROD31_R(r_re, r_im, wre, wim, t5,t6);\
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\
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BF_OPT(t1, t5, t5, t1);\
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BF_OPT(t6, t2, t2, t6);\
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TRANSFORM_POST_STORE( z, n );\
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}
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#define TRANSFORM_W01( z, n, w )\
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{\
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register FFTSample t1 asm("r5"),t2 asm("r6"),t5 asm("r7"),t6 asm("r8"),r_re asm("r9"),r_im asm("r10");\
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\
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{\
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register FFTSample wre asm("r4"),wim asm("r12");\
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asm volatile( "ldmia %[w], {%[wre], %[wim]}\n\t":[wre] "=r" (wre), [wim] "=r" (wim):[w] "r" (w));\
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z += n*2; /* z[o2] -- 2n * 2 since complex numbers */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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XPROD31_R(r_re, r_im, wre, wim, t1,t2);\
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\
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z += n; /* z[o3] */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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XNPROD31_R(r_re, r_im, wre, wim, t5,t6);\
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}\
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\
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BF_OPT(t1, t5, t5, t1);\
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BF_OPT(t6, t2, t2, t6);\
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TRANSFORM_POST_STORE( z, n );\
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}
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//static inline void TRANSFORM_W10(int32_t * z, unsigned int n, const int32_t * w)
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#define TRANSFORM_W10( z, n, w )\
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{\
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register FFTSample t1 asm("r5"),t2 asm("r6"),t5 asm("r7"),t6 asm("r8"),r_re asm("r9"),r_im asm("r10");\
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\
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{\
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register FFTSample wim asm("r4"),wre asm("r12");\
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asm volatile( "ldmia %[w], {%[wim], %[wre]}\n\t":[wim] "=r" (wim), [wre] "=r" (wre):[w] "r" (w));\
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z += n*2; /* z[o2] -- 2n * 2 since complex numbers */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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XPROD31_R(r_re, r_im, wre, wim, t1,t2);\
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\
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z += n; /* z[o3] */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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XNPROD31_R(r_re, r_im, wre, wim, t5,t6);\
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}\
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\
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BF_OPT(t1, t5, t5, t1);\
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BF_OPT(t6, t2, t2, t6);\
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TRANSFORM_POST_STORE( z, n );\
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}
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#define TRANSFORM_EQUAL( z, n )\
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{\
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register FFTSample t1 asm("r5"),t2 asm("r6"),t5 asm("r7"),t6 asm("r8"),r_re asm("r9"),r_im asm("r10");\
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\
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z += n*2; /* z[o2] -- 2n * 2 since complex numbers */\
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asm volatile( "ldmia %[my_z], {%[t5],%[t6]}\n\t":[t5] "=r" (t5), [t6] "=r" (t6):[my_z] "r" (z));\
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z += n; /* z[o3] */\
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asm volatile( "ldmia %[my_z], {%[r_re],%[r_im]}\n\t":[r_re] "=r" (r_re), [r_im] "=r" (r_im):[my_z] "r" (z));\
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\
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/**/\
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/*t2 = MULT32(cPI2_8, t5);*/\
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/*t1 = MULT31(cPI2_8, t6);*/\
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/*t6 = MULT31(cPI2_8, r_re);*/\
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/*t5 = MULT32(cPI2_8, r_im);*/\
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\
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/*t1 = ( t1 + (t2<<1) );*/\
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/*t2 = ( t1 - (t2<<2) );*/\
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/*t6 = ( t6 + (t5<<1) );*/\
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/*t5 = ( t6 - (t5<<2) );*/\
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/**/\
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t2 = MULT31(cPI2_8, t5);\
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t6 = MULT31(cPI2_8, t6);\
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r_re = MULT31(cPI2_8, r_re);\
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t5 = MULT31(cPI2_8, r_im);\
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\
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t1 = ( t6 + t2 );\
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t2 = ( t6 - t2 );\
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t6 = ( r_re + t5 );\
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t5 = ( r_re - t5 );\
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\
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BF_OPT(t1, t5, t5, t1);\
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BF_OPT(t6, t2, t2, t6);\
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TRANSFORM_POST_STORE( z, n );\
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}
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#define TRANSFORM_ZERO( z,n )\
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{\
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register FFTSample t1 asm("r5"),t2 asm("r6"),t5 asm("r7"),t6 asm("r8"),r_re asm("r9"),r_im asm("r10");\
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\
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z += n*2; /* z[o2] -- 2n * 2 since complex numbers */\
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asm volatile( "ldmia %[my_z], {%[t1],%[t2]}\n\t":[t1] "=r" (t1), [t2] "=r" (t2):[my_z] "r" (z));\
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z += n; /* z[o3] */\
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asm volatile( "ldmia %[my_z], {%[t5],%[t6]}\n\t":[t5] "=r" (t5), [t6] "=r" (t6):[my_z] "r" (z));\
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\
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BF_OPT(t1, t5, t5, t1);\
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BF_OPT(t6, t2, t2, t6);\
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TRANSFORM_POST_STORE( z, n );\
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}
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#define FFT_FFMPEG_INCL_OPTIMISED_FFT4
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#define fft4(z_arg)\
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{\
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/* input[0..7] -> output[0..7] */\
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fixed32 * m = (fixed32 *) ( ( z_arg ) );\
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/* load r1=z[0],r2=z[1],...,r8=z[7] */\
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asm volatile(\
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"ldmia %[z], {r1-r8}\n\t"\
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"add r1,r1,r3\n\t" /* r1 :=t1 */\
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"sub r3,r1,r3, lsl #1\n\t" /* r3 :=t3 */\
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"sub r7,r7,r5\n\t" /* r10:=t8 */\
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"add r5,r7,r5, lsl #1\n\t" /* r5 :=t6 */\
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\
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"add r1,r1,r5\n\t" /* r1 = o[0] */\
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"sub r5,r1,r5, lsl #1\n\t" /* r5 = o[4] */\
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\
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"add r2,r2,r4\n\t" /* r2 :=t2 */\
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"sub r4,r2,r4, lsl #1\n\t" /* r9 :=t4 */\
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\
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"add r12,r6,r8\n\t" /* r10:=t5 */\
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"sub r6,r6,r8\n\t" /* r6 :=t7 */\
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\
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"sub r8,r4,r7\n\t" /* r8 = o[7]*/ \
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"add r4,r4,r7\n\t" /* r4 = o[3]*/ \
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"sub r7,r3,r6\n\t" /* r7 = o[6]*/ \
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"add r3,r3,r6\n\t" /* r3 = o[2]*/ \
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"sub r6,r2,r12\n\t" /* r6 = o[5]*/ \
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"add r2,r2,r12\n\t" /* r2 = o[1]*/ \
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\
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"stmia %[z], {r1-r8}\n\t"\
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: /* outputs */\
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: /* inputs */ [z] "r" (m)\
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: /* clobbers */\
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"r1","r2","r3","r4","r5","r6","r7","r8","r12","memory"\
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);\
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}
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#define FFT_FFMPEG_INCL_OPTIMISED_FFT8
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/* The chunk of asm below is equivalent to the following:
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// first load in z[4].re thru z[7].im into local registers
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// ...
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BF_OPT2_REV(z[4].re, z[5].re, z[4].re, z[5].re); // x=a+b; y=x-(b<<1)
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BF_OPT2_REV(z[4].im, z[5].im, z[4].im, z[5].im);
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BF_REV (temp, z[7].re, z[6].re, z[7].re); // x=a+b; y=a-b;
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BF_REV (z[6].re, z[7].im, z[6].im, z[7].im);
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// save z[7].re and z[7].im as those are complete now
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// z[5].re and z[5].im are also complete now but save these later on
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BF(z[6].im, z[4].re, temp, z[4].re); // x=a-b; y=a+b
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BF_OPT(z[6].re, z[4].im, z[4].im, z[6].re); // y=a+b; x=y-(b<<1)
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// now load z[2].re and z[2].im
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// ...
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BF_OPT(z[6].re, z[2].re, z[2].re, z[6].re); // y=a+b; x=y-(b<<1)
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BF_OPT(z[6].im, z[2].im, z[2].im, z[6].im); // y=a+b; x=y-(b<<1)
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// Now save z[6].re and z[6].im, along with z[5].re and z[5].im
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// for efficiency. Also save z[2].re and z[2].im.
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// Now load z[0].re and z[0].im
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// ...
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BF_OPT(z[4].re, z[0].re, z[0].re, z[4].re); // y=a+b; x=y-(b<<1)
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BF_OPT(z[4].im, z[0].im, z[0].im, z[4].im); // y=a+b; x=y-(b<<1)
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// Finally save out z[4].re, z[4].im, z[0].re and z[0].im
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// ...
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*/
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static inline void fft8( FFTComplex * z )
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{
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fft4(z);
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{
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FFTSample temp;
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fixed32 * m4 = (fixed32 *)(&(z[4].re));
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asm volatile(
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"add %[z_ptr], %[z_ptr], #16\n\t" /* point to &z[2].re */
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/* read in z[4].re thru z[7].im */
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"ldmia %[z4_ptr]!, {r1,r2,r3,r4,r5,r6,r7,r8}\n\t"
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/* (now points one word past &z[7].im) */
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"add r1,r1,r3\n\t"
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"sub r3,r1,r3,lsl #1\n\t"
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"add r2,r2,r4\n\t"
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"sub r4,r2,r4,lsl #1\n\t"
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"add %[temp],r5,r7\n\t"
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"sub r7,r5,r7\n\t"
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"add r5,r6,r8\n\t"
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"sub r8,r6,r8\n\t"
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"stmdb %[z4_ptr]!, {r7,r8}\n\t" /* write z[7].re,z[7].im straight away */
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/* Note, registers r7 & r8 now free */
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"sub r6,%[temp],r1\n\t"
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"add r1,%[temp],r1\n\t"
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"add r2,r2,r5\n\t"
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"sub r5,r2,r5,lsl #1\n\t"
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"ldmia %[z_ptr],{r7,r8}\n\t" /* load z[2].re and z[2].im */
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"add r7,r7,r5\n\t"
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"sub r5,r7,r5,lsl #1\n\t"
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"add r8,r8,r6\n\t"
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"sub r6,r8,r6,lsl #1\n\t"
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/* write out z[5].re, z[5].im, z[6].re, z[6].im in one go*/
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"stmdb %[z4_ptr]!, {r3,r4,r5,r6}\n\t"
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"stmia %[z_ptr],{r7,r8}\n\t" /* write out z[2].re, z[2].im */
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"sub %[z_ptr],%[z_ptr], #16\n\t" /* point z_ptr back to &z[0].re */
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"ldmia %[z_ptr],{r7,r8}\n\t" /* load r[0].re, r[0].im */
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"add r7,r7,r1\n\t"
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"sub r1,r7,r1,lsl #1\n\t"
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"add r8,r8,r2\n\t"
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"sub r2,r8,r2,lsl #1\n\t"
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"stmia %[z_ptr],{r7,r8}\n\t" /* write out z[0].re, z[0].im */
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"stmdb %[z4_ptr], {r1,r2}\n\t" /* write out z[4].re, z[4].im */
|
|
: [z4_ptr] "+r" (m4), [z_ptr] "+r" (z), [temp] "=r" (temp)
|
|
:
|
|
: "r1","r2","r3","r4","r5","r6","r7","r8","memory"
|
|
);
|
|
}
|
|
|
|
z++;
|
|
TRANSFORM_EQUAL(z,2);
|
|
}
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|
|
|
|
|
#endif // CPU_ARM
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|
|