29644eb8f8
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5279 a1c6a512-1295-4272-9138-f99709370657
284 lines
6.8 KiB
ArmAsm
284 lines
6.8 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .init.text
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.global start
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start:
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#ifdef IRIVER_H100
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/* Platform: iRiver H1xx */
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move.w #0x2700,%sr
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move.l #MBAR+1,%d0
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movec.l %d0,%mbar
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move.l #MBAR2+1,%d0
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movec.l %d0,%mbar2
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lea MBAR,%a0
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lea MBAR2,%a1
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/* 64K DMA-capable SRAM at 0x10000000
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DMA is enabled and has priority in both banks
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x1000e001,%d0
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movec.l %d0,%rambar1
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/* 32K Non-DMA SRAM at 0x10010000
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x10010001,%d0
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movec.l %d0,%rambar0
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/* Chip select 0 - Flash ROM */
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move.l #0x00000000,%d0 /* CSAR0 - Base = 0x00000000 */
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move.l %d0,(0x080,%a0)
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move.l #0x001f0101,%d0 /* CSMR0 - 2M, All access, write protect */
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move.l %d0,(0x084,%a0)
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move.l #0x00000d80,%d0 /* CSCR0 - 3 wait states, 16 bits, no bursts */
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move.l %d0,(0x088,%a0)
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/* Chip select 1 - LCD controller */
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move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
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move.l %d0,(0x08c,%a0)
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move.l #0x0000007b,%d0 /* CSMR1 - 64K, Only data access */
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move.l %d0,(0x090,%a0)
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move.l #0x00002180,%d0 /* CSCR1 - 8 wait states, 16 bits, no bursts */
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move.l %d0,(0x094,%a0)
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/* Chip select 2 - ATA controller */
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move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */
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move.l %d0,(0x098,%a0)
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move.l #0x0000007b,%d0 /* CSMR2 - 64K, Only data access */
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move.l %d0,(0x09c,%a0)
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move.l #0x00000180,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states.
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We have to be careful with the access times,
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since IORDY isn't connected to the HDD. */
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/* Set up the DRAM controller. The refresh is based on the 11.2896MHz
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clock (5.6448MHz bus frequency). We haven't yet started the PLL */
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move.l #0x80050000,%d0
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move.l %d0,(0x100,%a0) /* DCR - Synchronous, 80 cycle refresh */
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move.l #0x3000a520,%d0
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move.l %d0,(0x108,%a0) /* DACR0 - Base 0x30000000, Banks on 23 and up,
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CAS latency 3, Refresh enable */
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move.l #0x01fc0001,%d0
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move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
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lea _iramcopy,%a2
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lea _iramstart,%a3
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lea _iramend,%a4
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.iramloop:
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cmp.l %a3,%a4
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beq .iramloopend
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move.w (%a2)+,(%a3)+
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bra .iramloop
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.iramloopend:
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lea _datacopy,%a2
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lea _datastart,%a3
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lea _dataend,%a4
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.dataloop:
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cmp.l %a3,%a4
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beq .dataloopend
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move.w (%a2)+,(%a3)+
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bra .dataloop
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.dataloopend:
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lea stackend,%sp
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jsr main
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.hoo:
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bra .hoo
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.section .resetvectors
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vectors:
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.long _stackend
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.long start
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#else
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/* Platform: Archos Jukebox
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* We begin with some tricks. If we have built our code to be loaded
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* via the standalone GDB stub, we will have out VBR at some other
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* location than 0x9000000. We must copy the trap vectors for the
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* GDB stub to our vector table.
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* If, on the other hand, we are running standalone we will have
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* the VBR at 0x9000000, and the copy will not do any harm.
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*/
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mov.l vbr_k,r1
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mov.l orig_vbr_k,r2
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/* Move the invalid instruction vector (4) */
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mov #4,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the invalid slot vector (6) */
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mov #6,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the bus error vector (9) */
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mov #9,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the DMA bus error vector (10) */
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mov #10,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the NMI vector as well (11) */
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mov #11,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the breakpoint trap vector (32) */
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mov #32,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the IO trap vector (33) */
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mov #33,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the serial Rx interrupt vector (105) */
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mov #105,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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/* Move the single step trap vector (127) */
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mov #127,r0
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shll2 r0
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mov.l @(r0,r2),r3
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mov.l r3,@(r0,r1)
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ldc r1,vbr
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/* Now let's get on with the normal business */
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mov.l stack_k,r15
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/* zero out bss */
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mov.l edata_k,r0
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mov.l end_k,r1
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mov #0,r2
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start_l:
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mov.l r2,@r0
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add #4,r0
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cmp/ge r1,r0
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bf start_l
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nop
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/* copy the .iram section */
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mov.l iramcopy_k,r0
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mov.l iram_k,r1
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mov.l iramend_k,r2
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copy_l:
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mov.l @r0,r3
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mov.l r3,@r1
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add #4,r0
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add #4,r1
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cmp/ge r2,r1
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bf copy_l
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nop
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/* copy the .data section, for rombased execution */
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mov.l datacopy_k,r0
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mov.l data_k,r1
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mov.l dataend_k,r2
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/* Don't copy if src and dest are equal */
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cmp/eq r0,r1
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bt nodatacopy
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copy_l2:
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mov.l @r0,r3
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mov.l r3,@r1
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add #4,r0
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add #4,r1
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cmp/ge r2,r1
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bf copy_l2
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nop
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nodatacopy:
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/* Munge the main thread stack */
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mov.l stack_k,r2
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mov.l deadbeef_k,r0
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mov.l stackbegin_k,r1
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munge_loop:
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mov.l r0,@r1
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add #4,r1
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cmp/ge r2,r1
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bf munge_loop
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nop
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mov #0,r0
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ldc r0,gbr
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! call the mainline
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mov.l main_k,r0
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jsr @r0
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nop
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.hoo:
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bra .hoo
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.align 2
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stack_k:
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.long _stackend
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stackbegin_k:
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.long _stackbegin
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deadbeef_k:
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.long 0xdeadbeef
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edata_k:
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.long _edata
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end_k:
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.long _end
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iramcopy_k:
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.long _iramcopy
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iram_k:
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.long _iramstart
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iramend_k:
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.long _iramend
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datacopy_k:
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.long _datacopy
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data_k:
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.long _datastart
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dataend_k:
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.long _dataend
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main_k:
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.long _main
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vbr_k:
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.long vectors
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orig_vbr_k:
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.long 0x9000000
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.section .resetvectors
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vectors:
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.long start
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.long _stackend
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.long start
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.long _stackend
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#endif
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