95e6043d5e
Massage the way it interfaces a bit to make things more flexible. The chroma_buf scheme on Sansa Connect and Creative ZVx calling the lcd_write_yuv420_lines implementation in lcd-as-memframe.S with five params with a chroma buffer that the function can't use wouldn't work anyway so just have them use the stock implementation (really, how was that working?). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31335 a1c6a512-1295-4272-9138-f99709370657
542 lines
17 KiB
C
542 lines
17 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Rockbox driver for Sansa e200 LCDs
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*
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* Based on reverse engineering done my MrH
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*
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* Copyright (c) 2006 Daniel Ankers
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "lcd.h"
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#include "lcd-target.h"
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/* Power and display status */
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extern bool lcd_on; /* lcd-memframe.c */
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static bool power_on = false; /* Is the power turned on? */
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/* Reverse Flag */
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#define R_DISP_CONTROL_NORMAL 0x0004
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#define R_DISP_CONTROL_REV 0x0000
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static unsigned short r_disp_control_rev = R_DISP_CONTROL_NORMAL;
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/* Flipping */
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#define R_DRV_OUTPUT_CONTROL_NORMAL 0x101b
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#define R_DRV_OUTPUT_CONTROL_FLIPPED 0x131b
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static unsigned short r_drv_output_control = R_DRV_OUTPUT_CONTROL_NORMAL;
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#define LCD_DATA_IN_GPIO GPIOB_INPUT_VAL
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#define LCD_DATA_IN_PIN 6
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#define LCD_DATA_OUT_GPIO GPIOB_OUTPUT_VAL
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#define LCD_DATA_OUT_PIN 7
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#define LCD_CLOCK_GPIO GPIOB_OUTPUT_VAL
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#define LCD_CLOCK_PIN 5
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#define LCD_CS_GPIO GPIOD_OUTPUT_VAL
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#define LCD_CS_PIN 6
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#define LCD_REG_0 (*(volatile unsigned long *)(0xc2000000))
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#define LCD_REG_1 (*(volatile unsigned long *)(0xc2000004))
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#define LCD_REG_2 (*(volatile unsigned long *)(0xc2000008))
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#define LCD_REG_3 (*(volatile unsigned long *)(0xc200000c))
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#define LCD_REG_4 (*(volatile unsigned long *)(0xc2000010))
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#define LCD_REG_5 (*(volatile unsigned long *)(0xc2000014))
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#define LCD_REG_6 (*(volatile unsigned long *)(0xc2000018))
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#define LCD_REG_7 (*(volatile unsigned long *)(0xc200001c))
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#define LCD_REG_8 (*(volatile unsigned long *)(0xc2000020))
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#define LCD_REG_9 (*(volatile unsigned long *)(0xc2000024))
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#define LCD_FB_BASE_REG (*(volatile unsigned long *)(0xc2000028))
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/* Taken from HD66789 datasheet and seems similar enough.
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Definitely a Renesas chip though with a perfect register index
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match but at least one bit seems to be set that that datasheet
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doesn't show. It says T.B.D. on the regmap anyway. */
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#define R_START_OSC 0x00
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#define R_DRV_OUTPUT_CONTROL 0x01
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#define R_DRV_WAVEFORM_CONTROL 0x02
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#define R_ENTRY_MODE 0x03
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#define R_COMPARE_REG1 0x04
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#define R_COMPARE_REG2 0x05
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#define R_DISP_CONTROL1 0x07
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#define R_DISP_CONTROL2 0x08
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#define R_DISP_CONTROL3 0x09
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#define R_FRAME_CYCLE_CONTROL 0x0b
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#define R_EXT_DISP_INTF_CONTROL 0x0c
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#define R_POWER_CONTROL1 0x10
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#define R_POWER_CONTROL2 0x11
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#define R_POWER_CONTROL3 0x12
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#define R_POWER_CONTROL4 0x13
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#define R_RAM_ADDR_SET 0x21
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#define R_RAM_READ_DATA 0x21
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#define R_RAM_WRITE_DATA 0x22
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#define R_RAM_WRITE_DATA_MASK1 0x23
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#define R_RAM_WRITE_DATA_MASK2 0x24
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#define R_GAMMA_FINE_ADJ_POS1 0x30
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#define R_GAMMA_FINE_ADJ_POS2 0x31
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#define R_GAMMA_FINE_ADJ_POS3 0x32
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#define R_GAMMA_GRAD_ADJ_POS 0x33
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#define R_GAMMA_FINE_ADJ_NEG1 0x34
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#define R_GAMMA_FINE_ADJ_NEG2 0x35
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#define R_GAMMA_FINE_ADJ_NEG3 0x36
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#define R_GAMMA_GRAD_ADJ_NEG 0x37
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#define R_GAMMA_AMP_ADJ_POS 0x38
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#define R_GAMMA_AMP_ADJ_NEG 0x39
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#define R_GATE_SCAN_START_POS 0x40
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#define R_VERT_SCROLL_CONTROL 0x41
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#define R_1ST_SCR_DRIVE_POS 0x42
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#define R_2ND_SCR_DRIVE_POS 0x43
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#define R_HORIZ_RAM_ADDR_POS 0x44
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#define R_VERT_RAM_ADDR_POS 0x45
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/* We don't know how to receive a DMA finished signal from the LCD controller.
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* To avoid problems with flickering, we double-buffer the framebuffer.
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* Align as in lcd-16bit.c and not cached. */
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fb_data lcd_driver_framebuffer[LCD_FBHEIGHT][LCD_FBWIDTH]
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__attribute__((aligned(16))) NOCACHEBSS_ATTR;
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#ifdef BOOTLOADER
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static void lcd_init_gpio(void)
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{
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GPIOB_ENABLE |= (1<<7);
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GPIOB_ENABLE |= (1<<5);
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GPIOB_OUTPUT_EN |= (1<<7);
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GPIOB_OUTPUT_EN |= (1<<5);
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GPIOD_ENABLE |= (1<<6);
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GPIOD_OUTPUT_EN |= (1<<6);
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}
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#endif
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static void lcd_bus_idle(void)
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{
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LCD_CLOCK_GPIO |= (1 << LCD_CLOCK_PIN);
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LCD_DATA_OUT_GPIO |= (1 << LCD_DATA_OUT_PIN);
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}
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static void lcd_send_byte(unsigned char byte)
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{
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int i;
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for (i = 7; i >=0 ; i--)
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{
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LCD_CLOCK_GPIO &= ~(1 << LCD_CLOCK_PIN);
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if ((byte >> i) & 1)
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{
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LCD_DATA_OUT_GPIO |= (1 << LCD_DATA_OUT_PIN);
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} else {
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LCD_DATA_OUT_GPIO &= ~(1 << LCD_DATA_OUT_PIN);
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}
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udelay(1);
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LCD_CLOCK_GPIO |= (1 << LCD_CLOCK_PIN);
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udelay(1);
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lcd_bus_idle();
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udelay(3);
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}
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}
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static void lcd_send_msg(unsigned char cmd, unsigned int data)
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{
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lcd_bus_idle();
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udelay(1);
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LCD_CS_GPIO &= ~(1 << LCD_CS_PIN);
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udelay(10);
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lcd_send_byte(cmd);
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lcd_send_byte((unsigned char)(data >> 8));
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lcd_send_byte((unsigned char)(data & 0xff));
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LCD_CS_GPIO |= (1 << LCD_CS_PIN);
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udelay(1);
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lcd_bus_idle();
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}
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static void lcd_write_reg(unsigned int reg, unsigned int data)
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{
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lcd_send_msg(0x70, reg);
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lcd_send_msg(0x72, data);
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}
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/* Run the powerup sequence for the driver IC */
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static void lcd_power_on(void)
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{
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/* Clear standby bit */
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lcd_write_reg(R_POWER_CONTROL1, 0x0000);
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/** Power ON Sequence **/
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lcd_write_reg(R_START_OSC, 0x0001);
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/* 10ms or more for oscillation circuit to stabilize */
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sleep(HZ/50);
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/* SAP2-0=100, BT2-0=100, AP2-0=100, DK=1, SLP=0, STB=0 */
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lcd_write_reg(R_POWER_CONTROL1, 0x4444);
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/* DC12-10=000, DC2-0=000, VC2-0=001 */
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lcd_write_reg(R_POWER_CONTROL2, 0x0001);
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/* PON=0, VRH3-0=0011 */
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lcd_write_reg(R_POWER_CONTROL3, 0x0003);
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/* VCOMG=0, VDV4-0=10001, VCM3-0=11001 */
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lcd_write_reg(R_POWER_CONTROL4, 0x1119);
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/* PON=1, VRH3-0=0011 */
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lcd_write_reg(R_POWER_CONTROL3, 0x0013);
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sleep(HZ/25);
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/* SAP2-0=100, BT2-0=100, AP2-0=100, DK=0, SLP=0, STB=0 */
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lcd_write_reg(R_POWER_CONTROL1, 0x4440);
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/* VCOMG=1, VDV4-0=10001, VCM3-0=11001 */
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lcd_write_reg(R_POWER_CONTROL4, 0x3119);
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sleep(HZ/6);
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/* VSPL=0, HSPL=0, DPL=1, EPL=0, SM=0, GS=x, SS=x, NL4-0=11011 */
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lcd_write_reg(R_DRV_OUTPUT_CONTROL, r_drv_output_control);
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/* FLD=0, FLD0=1, B/C=1, EOR=1, NW5-0=000000 */
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lcd_write_reg(R_DRV_WAVEFORM_CONTROL, 0x0700);
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/* TRI=0, DFM1-0=11, BGR=0, HWM=1, ID1-0=10, AM=0, LG2-0=000
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* AM: horizontal update direction
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* ID1-0: H decrement, V increment
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*/
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lcd_write_reg(R_ENTRY_MODE, 0x6020);
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lcd_write_reg(R_COMPARE_REG1, 0x0000);
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lcd_write_reg(R_COMPARE_REG2, 0x0000);
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/* FP3-0=0010, BP3-0=0010 */
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lcd_write_reg(R_DISP_CONTROL2, 0x0202);
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/* PTG1-0=00 (normal scan), ISC3-0=0000 (ignored) */
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lcd_write_reg(R_DISP_CONTROL3, 0x0000);
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/* NO2-0=01, SDT1-0=00, EQ1-0=01, DIV1-0=00, RTN3-0=0000 */
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lcd_write_reg(R_FRAME_CYCLE_CONTROL, 0x4400);
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/* RM=1, DM1-0=01, RIM1-0=00 */
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lcd_write_reg(R_EXT_DISP_INTF_CONTROL, 0x0110);
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/* SCN4-0=00000 - G1 if GS=0, G240 if GS=1 */
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lcd_write_reg(R_GATE_SCAN_START_POS, 0x0000);
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/* VL7-0=00000000 (0 lines) */
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lcd_write_reg(R_VERT_SCROLL_CONTROL, 0x0000);
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/* SE17-10=219, SS17-10=0 - 220 gates */
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lcd_write_reg(R_1ST_SCR_DRIVE_POS, (219 << 8));
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/* SE27-10=0, SS27-10=0 - no second screen */
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lcd_write_reg(R_2ND_SCR_DRIVE_POS, 0x0000);
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/* HEA=175, HSA=0 = H window from 0-175 */
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lcd_write_reg(R_HORIZ_RAM_ADDR_POS, (175 << 8));
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/* VEA=219, VSA=0 = V window from 0-219 */
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lcd_write_reg(R_VERT_RAM_ADDR_POS, (219 << 8));
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/* PKP12-10=000, PKP02-00=000 */
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lcd_write_reg(R_GAMMA_FINE_ADJ_POS1, 0x0000);
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/* PKP32-30=111, PKP22-20=100 */
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lcd_write_reg(R_GAMMA_FINE_ADJ_POS2, 0x0704);
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/* PKP52-50=001, PKP42-40=111 */
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lcd_write_reg(R_GAMMA_FINE_ADJ_POS3, 0x0107);
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/* PRP12-10=111, PRP02-00=100 */
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lcd_write_reg(R_GAMMA_GRAD_ADJ_POS, 0x0704);
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/* PKN12-10=001, PKN02-00=111 */
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lcd_write_reg(R_GAMMA_FINE_ADJ_NEG1, 0x0107);
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/* PKN32-30=000, PKN22-20=010 */
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lcd_write_reg(R_GAMMA_FINE_ADJ_NEG2, 0x0002);
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/* PKN52-50=111, PKN42-40=111 */
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lcd_write_reg(R_GAMMA_FINE_ADJ_NEG3, 0x0707);
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/* PRN12-10=101, PRN02-00=011 */
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lcd_write_reg(R_GAMMA_GRAD_ADJ_NEG, 0x0503);
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/* VRP14-10=00000, VRP03-00=0000 */
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lcd_write_reg(R_GAMMA_AMP_ADJ_POS, 0x0000);
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/* WRN14-10=00000, VRN03-00=0000 */
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lcd_write_reg(R_GAMMA_AMP_ADJ_NEG, 0x0000);
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/* AD15-0=175 (upper right corner) */
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lcd_write_reg(R_RAM_ADDR_SET, 175);
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/* RM=1, DM1-0=01, RIM1-0=00 */
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lcd_write_reg(R_EXT_DISP_INTF_CONTROL, 0x0110);
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power_on = true;
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}
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/* Run the display on sequence for the driver IC */
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static void lcd_display_on(void)
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{
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if (!power_on)
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{
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/* Power has been turned off so full reinit is needed */
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lcd_power_on();
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}
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else
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{
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/* Restore what we fiddled with when turning display off */
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/* PON=1, VRH3-0=0011 */
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lcd_write_reg(R_POWER_CONTROL3, 0x0013);
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/* NO2-0=01, SDT1-0=00, EQ1-0=01, DIV1-0=00, RTN3-0=0000 */
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lcd_write_reg(R_FRAME_CYCLE_CONTROL, 0x4400);
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/* VCOMG=1, VDV4-0=10001, VCM3-0=11001 */
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lcd_write_reg(R_POWER_CONTROL4, 0x3119);
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}
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/* SAP2-0=100, BT2-0=111, AP2-0=100, DK=1, SLP=0, STB=0 */
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lcd_write_reg(R_POWER_CONTROL1, 0x4740);
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sleep(HZ/25);
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/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=1, GON=0, DTE=0, CL=0,
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REV=x, D1-0=01 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0041 | r_disp_control_rev);
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sleep(HZ/30);
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/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=1, GON=1, DTE=0, CL=0,
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REV=x, D1-0=01 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0061 | r_disp_control_rev);
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/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=1, GON=1, DTE=0, CL=0,
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REV=x, D1-0=11 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0063 | r_disp_control_rev);
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sleep(HZ/30);
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/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=1, GON=1, DTE=1, CL=0,
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REV=x, D1-0=11 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0073 | r_disp_control_rev);
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/* Go into write data mode */
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lcd_send_msg(0x70, R_RAM_WRITE_DATA);
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/* tell that we're on now */
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lcd_on = true;
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}
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#if defined(HAVE_LCD_ENABLE) || defined(HAVE_LCD_SLEEP)
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/* Turn off visible display operations */
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static void lcd_display_off(void)
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{
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/* block drawing operations and changing of first */
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lcd_on = false;
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/* NO2-0=01, SDT1-0=00, EQ1-0=00, DIV1-0=00, RTN3-0=0000 */
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lcd_write_reg(R_FRAME_CYCLE_CONTROL, 0x4000);
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/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=1, GON=1, DTE=1, CL=0,
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REV=x, D1-0=10 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0072 | r_disp_control_rev);
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sleep(HZ/25);
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/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=1, GON=1, DTE=0, CL=0,
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REV=x, D1-0=10 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0062 | r_disp_control_rev);
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sleep(HZ/25);
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/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=0, GON=0, DTE=0, CL=0,
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REV=0, D1-0=00 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0000);
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/* SAP2-0=000, BT2-0=000, AP2-0=000, DK=0, SLP=0, STBY=0 */
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lcd_write_reg(R_POWER_CONTROL1, 0x0000);
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/* PON=0, VRH3-0=0011 */
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lcd_write_reg(R_POWER_CONTROL3, 0x0003);
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/* VCOMG=0, VDV4-0=10001, VCM4-0=11001 */
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lcd_write_reg(R_POWER_CONTROL4, 0x1119);
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}
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#endif
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void lcd_init_device(void)
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{
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/* All this is magic worked out by MrH */
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/* Stop any DMA which is in progress */
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LCD_REG_6 &= ~1;
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udelay(100000);
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#ifdef BOOTLOADER /* Bother at all to do this again? */
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/* Init GPIO ports */
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lcd_init_gpio();
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/* Controller init */
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GPO32_ENABLE |= (1 << 28);
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GPO32_VAL &= ~(1 << 28);
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DEV_INIT1 = ( (DEV_INIT1 & 0x03ffffff) | (0x15 << 26) );
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outl(((inl(0x70000014) & (0x0fffffff)) | (0x5 << 28)), 0x70000014);
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outl((inl(0x70000020) & ~(0x3 << 10)), 0x70000020);
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DEV_EN |= DEV_LCD; /* Enable controller */
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outl(0x6, 0x600060d0);
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DEV_RS |= DEV_LCD; /* Reset controller */
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outl((inl(0x70000020) & ~(1 << 14)), 0x70000020);
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lcd_bus_idle();
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DEV_RS &=~DEV_LCD; /* Clear reset */
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udelay(1000);
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LCD_REG_0 = (LCD_REG_0 & (0x00ffffff)) | (0x22 << 24);
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LCD_REG_0 = (LCD_REG_0 & (0xff00ffff)) | (0x14 << 16);
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LCD_REG_0 = (LCD_REG_0 & (0xffffc0ff)) | (0x3 << 8);
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LCD_REG_0 = (LCD_REG_0 & (0xffffffc0)) | (0xa);
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LCD_REG_1 &= 0x00ffffff;
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LCD_REG_1 &= 0xff00ffff;
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LCD_REG_1 = (LCD_REG_1 & 0xffff03ff) | (0x2 << 10);
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LCD_REG_1 = (LCD_REG_1 & 0xfffffc00) | (0xdd);
|
|
|
|
LCD_REG_2 |= (1 << 5);
|
|
LCD_REG_2 |= (1 << 6);
|
|
LCD_REG_2 = (LCD_REG_2 & 0xfffffcff) | (0x2 << 8);
|
|
|
|
LCD_REG_7 &= (0xf800ffff);
|
|
LCD_REG_7 &= (0xfffff800);
|
|
|
|
LCD_REG_8 = (LCD_REG_8 & (0xf800ffff)) | (0xb0 << 16);
|
|
LCD_REG_8 = (LCD_REG_8 & (0xfffff800)) | (0xdc); /* X-Y Geometry? */
|
|
|
|
LCD_REG_5 |= 0xc;
|
|
LCD_REG_5 = (LCD_REG_5 & ~(0x70)) | (0x3 << 4);
|
|
LCD_REG_5 |= 2;
|
|
|
|
LCD_REG_6 &= ~(1 << 15);
|
|
LCD_REG_6 |= (0xe00);
|
|
LCD_REG_6 = (LCD_REG_6 & (0xffffff1f)) | (0x4 << 5);
|
|
LCD_REG_6 |= (1 << 4);
|
|
|
|
LCD_REG_5 &= ~(1 << 7);
|
|
/* lcd_driver_framebuffer is uncached therefore at the physical address */
|
|
LCD_FB_BASE_REG = (long)lcd_driver_framebuffer;
|
|
|
|
udelay(100000);
|
|
|
|
/* LCD init */
|
|
/* Pull RESET low, then high to reset driver IC */
|
|
GPO32_VAL &= ~(1 << 28);
|
|
udelay(10000);
|
|
GPO32_VAL |= (1 << 28);
|
|
udelay(10000);
|
|
|
|
lcd_display_on();
|
|
#else
|
|
/* Power and display already ON - switch framebuffer address and reset
|
|
settings */
|
|
/* lcd_driver_framebuffer is uncached therefore at the physical address */
|
|
LCD_FB_BASE_REG = (long)lcd_driver_framebuffer;
|
|
|
|
power_on = true;
|
|
lcd_on = true;
|
|
|
|
lcd_set_invert_display(false);
|
|
lcd_set_flip(false);
|
|
#endif
|
|
|
|
LCD_REG_6 |= 1; /* Start DMA */
|
|
}
|
|
|
|
#if defined(HAVE_LCD_ENABLE)
|
|
void lcd_enable(bool on)
|
|
{
|
|
if (on == lcd_on)
|
|
return;
|
|
|
|
if (on)
|
|
{
|
|
DEV_EN |= DEV_LCD; /* Enable LCD controller */
|
|
lcd_display_on(); /* Turn on display */
|
|
lcd_update(); /* Resync display */
|
|
send_event(LCD_EVENT_ACTIVATION, NULL);
|
|
LCD_REG_6 |= 1; /* Restart DMA */
|
|
sleep(HZ/50); /* Wait for a frame to be written */
|
|
}
|
|
else
|
|
{
|
|
LCD_REG_6 &= ~1; /* Disable DMA */
|
|
sleep(HZ/50); /* Wait for dma end (assuming 50Hz) */
|
|
lcd_display_off(); /* Turn off display */
|
|
DEV_EN &= ~DEV_LCD; /* Disable LCD controller */
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if defined(HAVE_LCD_SLEEP)
|
|
void lcd_sleep(void)
|
|
{
|
|
LCD_REG_6 &= ~1;
|
|
sleep(HZ/50);
|
|
|
|
if (power_on)
|
|
{
|
|
/* Turn off display */
|
|
if (lcd_on)
|
|
lcd_display_off();
|
|
power_on = false;
|
|
}
|
|
|
|
/* Set standby mode */
|
|
/* SAP2-0=000, BT2-0=000, AP2-0=000, DK=0, SLP=0, STB=1 */
|
|
lcd_write_reg(R_POWER_CONTROL1, 0x0001);
|
|
}
|
|
#endif
|
|
|
|
/*** hardware configuration ***/
|
|
|
|
void lcd_set_contrast(int val)
|
|
{
|
|
/* TODO: Implement lcd_set_contrast() */
|
|
(void)val;
|
|
}
|
|
|
|
void lcd_set_invert_display(bool yesno)
|
|
{
|
|
bool dma_on = LCD_REG_6 & 1;
|
|
|
|
if (dma_on)
|
|
{
|
|
LCD_REG_6 &= ~1; /* Disable DMA */
|
|
sleep(HZ/50); /* Wait for dma end (assuming 50Hz) */
|
|
DEV_EN &= ~DEV_LCD; /* Disable LCD controller */
|
|
}
|
|
|
|
r_disp_control_rev = yesno ? R_DISP_CONTROL_REV :
|
|
R_DISP_CONTROL_NORMAL;
|
|
|
|
if (lcd_on)
|
|
{
|
|
/* PT1-0=00, VLE2-1=00, SPT=0, IB6(??)=1, GON=1, CL=0,
|
|
DTE=1, REV=x, D1-0=11 */
|
|
lcd_write_reg(R_DISP_CONTROL1, 0x0073 | r_disp_control_rev);
|
|
}
|
|
|
|
if (dma_on)
|
|
{
|
|
DEV_EN |= DEV_LCD; /* Enable LCD controller */
|
|
lcd_send_msg(0x70, R_RAM_WRITE_DATA); /* Set to RAM write mode */
|
|
LCD_REG_6 |= 1; /* Restart DMA */
|
|
}
|
|
}
|
|
|
|
/* turn the display upside down (call lcd_update() afterwards) */
|
|
void lcd_set_flip(bool yesno)
|
|
{
|
|
bool dma_on = LCD_REG_6 & 1;
|
|
|
|
if (dma_on)
|
|
{
|
|
LCD_REG_6 &= ~1; /* Disable DMA */
|
|
sleep(HZ/50); /* Wait for dma end (assuming 50Hz) */
|
|
DEV_EN &= ~DEV_LCD; /* Disable LCD controller */
|
|
}
|
|
|
|
r_drv_output_control = yesno ? R_DRV_OUTPUT_CONTROL_FLIPPED :
|
|
R_DRV_OUTPUT_CONTROL_NORMAL;
|
|
|
|
if (power_on)
|
|
{
|
|
/* VSPL=0, HSPL=0, DPL=1, EPL=0, SM=0, GS=x, SS=x,
|
|
NL4-0=11011 (G1-G224) */
|
|
lcd_write_reg(R_DRV_OUTPUT_CONTROL, r_drv_output_control);
|
|
}
|
|
|
|
if (dma_on)
|
|
{
|
|
DEV_EN |= DEV_LCD; /* Enable LCD controller */
|
|
lcd_send_msg(0x70, R_RAM_WRITE_DATA); /* Set to RAM write mode */
|
|
LCD_REG_6 |= 1; /* Restart DMA */
|
|
}
|
|
}
|