722e24a76a
Implemented scheme:
ARM AHB APB
Normal 50 50 50 MHz
Max 200 100 50 MHz
Frequency scaling is disabled on rk27generic due to too
slow lcd updates when running with 50MHz AHB.
battery_bench shows ~1h runtime improvement on hifiman.
Change-Id: I2c6f8acf6d4570c4e14f5bcc72280b51ce13c408
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 Rafaël Carré
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* Copyright (C) 2011 Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#include "panic.h"
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void udelay(unsigned usecs);
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static inline void mdelay(unsigned msecs)
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{
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udelay(1000 * msecs);
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}
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/* Datasheet is very cryptic how to use this.
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* With cache enabled it simpy hangs here
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*/
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static inline void core_sleep(void)
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{
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enable_irq();
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/* SCU_CPUPD = 0xdeedbabe; */
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}
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/* Write DCache back to RAM for the given range and remove cache lines
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* from DCache afterwards */
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void commit_discard_dcache_range(const void *base, unsigned int size);
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static inline void commit_dcache(void) {}
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void commit_discard_dcache(void);
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void commit_discard_idcache(void);
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#define CPUFREQ_DEFAULT 50000000
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#define CPUFREQ_NORMAL 50000000
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#define CPUFREQ_MAX 200000000
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#endif /* SYSTEM_TARGET_H */
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