b93667b306
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17742 a1c6a512-1295-4272-9138-f99709370657
302 lines
8.2 KiB
C
302 lines
8.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Dave Chapman
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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/* Externally defined interrupt handlers */
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extern void TIMER(void);
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extern void ADC(void);
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void irq(void)
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{
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int irq = IREQ & 0x7fffffff;
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CREQ = irq; /* Clears the corresponding IRQ status */
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if (irq & TIMER0_IRQ_MASK)
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TIMER();
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else if (irq & ADC_IRQ_MASK)
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ADC();
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else
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panicf("Unhandled IRQ 0x%08X", irq);
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}
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void fiq_handler(void)
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{
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/* TODO */
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}
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void system_reboot(void)
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{
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}
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/* TODO - these should live in the target-specific directories and
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once we understand what all the GPIO pins do, move the init to the
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specific driver for that hardware. For now, we just perform the
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same GPIO init as the original firmware - this makes it easier to
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investigate what the GPIO pins do.
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*/
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#ifdef LOGIK_DAX
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static void gpio_init(void)
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{
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/* Do what the original firmware does */
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GPIOD_FUNC = 0;
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GPIOD_DIR = 0x3f0;
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GPIOD = 0xe0;
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GPIOE_FUNC = 0;
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GPIOE_DIR = 0xe0;
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GPIOE = 0;
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GPIOA_FUNC = 0;
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GPIOA_DIR = 0xffff1000; /* 0 - 0xf000 */
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GPIOA = 0x1080;
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GPIOB_FUNC = 0x16a3;
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GPIOB_DIR = 0x6ffff;
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GPIOB = 0;
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GPIOC_FUNC = 1;
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GPIOC_DIR = 0x03ffffff; /* mvn r2, 0xfc000000 */
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GPIOC = 0;
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}
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#elif defined(IAUDIO_7)
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static void gpio_init(void)
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{
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/* Do what the original firmware does */
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GPIOA_FUNC = 0;
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GPIOB_FUNC = 0x1623;
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GPIOC_FUNC = 1;
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GPIOD_FUNC = 0;
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GPIOE_FUNC = 0;
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GPIOA = 0x30;
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GPIOB = 0x80000;
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GPIOC = 0;
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GPIOD = 0x180;
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GPIOE = 0;
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GPIOA_DIR = 0x84b0
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GPIOB_DIR = 0x80800;
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GPIOC_DIR = 0x2000000;
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GPIOD_DIR = 0x3e3;
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GPIOE_DIR = 0x88;
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}
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#elif defined(SANSA_M200)
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static void gpio_init(void)
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{
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/* TODO - Implement for M200 */
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}
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#elif defined(SANSA_C100)
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static void gpio_init(void)
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{
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/* Do what the original firmware does */
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GPIOA_FUNC = 0;
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GPIOB_FUNC = 0x16A3;
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GPIOC_FUNC = 1;
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GPIOD_FUNC |= 2;
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GPIOE_FUNC = 0;
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GPIOA_DIR = 0xFFFF0E00;
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GPIOB_DIR = 0x6FFFF;
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GPIOC_DIR = 0x03FFFFFF;
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GPIOD_DIR = 0x3F7;
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GPIOE_DIR = 0x9B;
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GPIOA = 0x80;
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GPIOB = 0;
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GPIOC = 0;
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GPIOD |= 0xC0;
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GPIOE = 0x9B;
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}
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#endif
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/* Second function called in the original firmware's startup code - we just
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set up the clocks in the same way as the original firmware for now. */
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static void clock_init(void)
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{
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unsigned int i;
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/* STP = 0x1, PW = 0x04 , HLD = 0x0 */
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CSCFG3 = (CSCFG3 &~ 0x3fff) | 0x820;
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/* XIN=External main, Fcpu=Fsys, BCKDIV=1 (Fbus = Fsys / 2) */
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CLKCTRL = (CLKCTRL & ~0xff) | 0x14;
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if (BMI & 0x20)
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PCLKCFG0 = 0xc82d7000; /* EN1 = 1, XIN=Ext. main, DIV1 = 0x2d, P1 = 1 */
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else
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PCLKCFG0 = 0xc8ba7000; /* EN1 = 1, XIN=Ext. main, DIV1 = 0xba, P1 = 1 */
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MCFG |= 0x2000;
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#ifdef LOGIK_DAX
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/* Only seen in the Logik DAX original firmware */
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SDCFG = (SDCFG & ~0x7000) | 0x2000;
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#endif
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/* Disable PLL */
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PLL0CFG |= 0x80000000;
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/* Enable PLL, M=0xcf, P=0x13. m=M+8, p=P+2, S = 0
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Fout = (215/21)*12MHz = 122857142Hz */
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PLL0CFG = 0x0000cf13;
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i = 8000;
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while (--i) {};
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/* Enable PLL0 */
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CLKDIVC = 0x81000000;
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/* Fsys = PLL0, Fcpu = Fsys, Fbus=Fsys / 2 */
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CLKCTRL = 0x80000010;
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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);
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}
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static void cpu_init(void)
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{
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/* Memory protection - see page 48 of ARM946 TRM
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http://infocenter.arm.com/help/topic/com.arm.doc.ddi0201d/DDI0201D_arm946es_r1p1_trm.pdf
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*/
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asm volatile (
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/* Region 0 - addr=0, size=4GB, enabled */
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"mov r0, #0x3f \n\t"
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"mcr p15, 0, r0, c6, c0, 0 \n\t"
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"mcr p15, 0, r0, c6, c0, 1 \n\t"
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#if defined(LOGIK_DAX) || defined(SANSA_C100)
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/* Address region 1 - addr 0x2fff0000, size=64KB, enabled*/
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"ldr r0, =0x2fff001f \n\t"
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#elif defined(IAUDIO_7)
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/* Address region 1 - addr 0x20000000, size=8KB, enabled*/
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"mov r0, #0x19 \n\t"
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"add r0, r0, #0x20000000 \n\t"
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#elif defined(SANSA_M200)
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/* Address region 1 - addr 0x20000000, size=256MB, enabled*/
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"mov r0, #0x37 \n\t"
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"add r0, r0, #0x20000000 \n\t"
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#endif
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"mcr p15, 0, r0, c6, c1, 0 \n\t"
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"mcr p15, 0, r0, c6, c1, 1 \n\t"
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/* Address region 2 - addr 0x30000000, size=256MB, enabled*/
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"mov r0, #0x37 \n\t"
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"add r0, r0, #0x30000000 \n\t"
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"mcr p15, 0, r0, c6, c2, 0 \n\t"
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"mcr p15, 0, r0, c6, c2, 1 \n\t"
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/* Address region 2 - addr 0x40000000, size=512MB, enabled*/
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"mov r0, #0x39 \n\t"
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"add r0, r0, #0x40000000 \n\t"
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"mcr p15, 0, r0, c6, c3, 0 \n\t"
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"mcr p15, 0, r0, c6, c3, 1 \n\t"
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/* Address region 4 - addr 0x60000000, size=256MB, enabled*/
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"mov r0, #0x37 \n\t"
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"add r0, r0, #0x60000000 \n\t"
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"mcr p15, 0, r0, c6, c4, 0 \n\t"
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"mcr p15, 0, r0, c6, c4, 1 \n\t"
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/* Address region 5 - addr 0x10000000, size=256MB, enabled*/
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"mov r0, #0x37 \n\t"
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"add r0, r0, #0x10000000 \n\t"
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"mcr p15, 0, r0, c6, c5, 0 \n\t"
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"mcr p15, 0, r0, c6, c5, 1 \n\t"
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/* Address region 6 - addr 0x80000000, size=2GB, enabled*/
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"mov r0, #0x37 \n\t"
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"add r0, r0, #0x80000006 \n\t"
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"mcr p15, 0, r0, c6, c6, 0 \n\t"
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"mcr p15, 0, r0, c6, c6, 1 \n\t"
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/* Address region 7 - addr 0x3000f000, size=4KB, enabled*/
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"ldr r0, =0x3000f017 \n\t"
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"mcr p15, 0, r0, c6, c7, 0 \n\t"
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"mcr p15, 0, r0, c6, c7, 1 \n\t"
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/* Register 5 - Access Permission Registers */
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"ldr r0, =0xffff \n\t"
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"mcr p15, 0, r0, c5, c0, 0 \n\t" /* write data access permission bits */
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"mcr p15, 0, r0, c5, c0, 1 \n\t" /* write instruction access permission bits */
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"mov r0, #0xa7 \n\t"
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"mcr p15, 0, r0, c3, c0, 0 \n\t" /* set write buffer control register */
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#if defined(LOGIK_DAX) || defined(SANSA_C100)
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"mov r0, #0xa5 \n\t"
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#elif defined(IAUDIO_7) || defined(SANSA_M200)
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"mov r0, #0xa7 \n\t"
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#elif
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#error NOT DEFINED FOR THIS TARGET!
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#endif
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"mcr p15, 0, r0, c2, c0, 0 \n\t"
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"mcr p15, 0, r0, c2, c0, 1 \n\t"
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"mov r0, #0xa0000006 \n\t"
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"mcr p15, 0, r0, c9, c1, 0 \n\t"
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"ldr r1, =0x1107d \n\t"
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"mov r0, #0x0 \n\t"
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"mcr p15, 0, r0, c7, c5, 0 \n\t" /* Flush instruction cache */
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"mcr p15, 0, r0, c7, c6, 0 \n\t" /* Flush data cache */
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"mcr p15, 0, r1, c1, c0, 0 \n\t" /* CPU control bits */
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: : : "r0", "r1"
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);
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}
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void system_init(void)
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{
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/* mask all interrupts */
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IEN = 0;
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/* Set all interrupts as IRQ for now - some may need to be FIQ in future */
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IRQSEL = 0xffffffff;
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/* Set master enable bit */
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IEN = 0x80000000;
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cpu_init();
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clock_init();
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gpio_init();
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enable_irq();
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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}
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#endif
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