780f79e7a4
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11504 a1c6a512-1295-4272-9138-f99709370657
426 lines
11 KiB
C
426 lines
11 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SYSTEM_H__
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#define __SYSTEM_H__
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#include "cpu.h"
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#include "stdbool.h"
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extern void system_reboot (void);
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extern void system_init(void);
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extern long cpu_frequency;
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#ifdef CPU_PP
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#define inl(a) (*(volatile unsigned long *) (a))
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#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
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#define inb(a) (*(volatile unsigned char *) (a))
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#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
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#define inw(a) (*(volatile unsigned short *) (a))
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#define outw(a,b) (*(volatile unsigned short *) (b) = (a))
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extern unsigned int ipod_hw_rev;
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static inline void udelay(unsigned usecs)
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{
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unsigned start = USEC_TIMER;
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while ((USEC_TIMER - start) < usecs);
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}
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unsigned int current_core(void);
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#endif
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struct flash_header {
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unsigned long magic;
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unsigned long length;
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char version[32];
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};
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bool detect_flashed_rockbox(void);
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#define FREQ cpu_frequency
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void set_cpu_frequency(long frequency);
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void cpu_boost(bool on_off);
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void cpu_idle_mode(bool on_off);
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int get_cpu_boost_counter(void);
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#if MEM > 1
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#define CPU_BOOST_TRACKING
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#endif
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#ifdef CPU_BOOST_TRACKING
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void cpu_boost_id(bool on_off, char id);
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const char *get_cpu_boost_tracker(void);
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/* CPU boost ID chars, in alphabetical order */
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#define CPUBOOSTID_PLAYBACK_AUDIO 'A'
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#define CPUBOOSTID_TAGTREE 'a'
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#define CPUBOOSTID_BACKLIGHT 'b'
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#define CPUBOOSTID_PLAYBACK_CODEC 'c'
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#define CPUBOOSTID_DIRCACHE 'd'
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#define CPUBOOSTID_MAININIT 'i'
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#define CPUBOOSTID_DEBUGMENU_MANUAL 'm'
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#define CPUBOOSTID_PLAYLIST 'P'
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#define CPUBOOSTID_PCMBUF 'p'
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#define CPUBOOSTID_PCMRECORD 'R'
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#define CPUBOOSTID_TREE 'r'
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#define CPUBOOSTID_TALK 'T'
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#define CPUBOOSTID_TAGCACHE 't'
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#define CPUBOOSTID_PLAYBACK_VOICE 'v'
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#else
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#define cpu_boost_id(on_off,id) cpu_boost(on_off)
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#endif
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#else
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#define FREQ CPU_FREQ
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#define set_cpu_frequency(frequency)
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#define cpu_boost(on_off)
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#define cpu_boost_id(on_off, id)
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#define cpu_idle_mode(on_off)
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#define get_cpu_boost_counter()
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#define get_cpu_boost_tracker()
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#endif
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#define BAUDRATE 9600
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#ifndef NULL
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#define NULL ((void*)0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a)<(b))?(a):(b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a)>(b))?(a):(b))
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#endif
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/* return number of elements in array a */
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#define ARRAYLEN(a) (sizeof(a)/sizeof((a)[0]))
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/* return p incremented by specified number of bytes */
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#define SKIPBYTES(p, count) ((typeof (p))((char *)(p) + (count)))
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#define P2_M1(p2) ((1 << (p2))-1)
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/* align up or down to nearest 2^p2 */
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#define ALIGN_DOWN_P2(n, p2) ((n) & ~P2_M1(p2))
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#define ALIGN_UP_P2(n, p2) ALIGN_DOWN_P2((n) + P2_M1(p2),p2)
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/* align up or down to nearest integer multiple of a */
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#define ALIGN_DOWN(n, a) ((n)/(a)*(a))
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#define ALIGN_UP(n, a) ALIGN_DOWN((n)+((a)-1),a)
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/* live endianness conversion */
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#ifdef ROCKBOX_LITTLE_ENDIAN
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#define letoh16(x) (x)
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#define letoh32(x) (x)
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#define htole16(x) (x)
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#define htole32(x) (x)
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#define betoh16(x) swap16(x)
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#define betoh32(x) swap32(x)
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#define htobe16(x) swap16(x)
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#define htobe32(x) swap32(x)
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#define swap_odd_even_be32(x) (x)
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#define swap_odd_even_le32(x) swap_odd_even32(x)
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#else
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#define letoh16(x) swap16(x)
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#define letoh32(x) swap32(x)
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#define htole16(x) swap16(x)
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#define htole32(x) swap32(x)
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#define betoh16(x) (x)
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#define betoh32(x) (x)
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#define htobe16(x) (x)
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#define htobe32(x) (x)
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#define swap_odd_even_be32(x) swap_odd_even32(x)
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#define swap_odd_even_le32(x) (x)
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#endif
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/* static endianness conversion */
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#define SWAP_16(x) ((typeof(x))(unsigned short)(((unsigned short)(x) >> 8) | \
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((unsigned short)(x) << 8)))
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#define SWAP_32(x) ((typeof(x))(unsigned long)( ((unsigned long)(x) >> 24) | \
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(((unsigned long)(x) & 0xff0000ul) >> 8) | \
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(((unsigned long)(x) & 0xff00ul) << 8) | \
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((unsigned long)(x) << 24)))
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#ifdef ROCKBOX_LITTLE_ENDIAN
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#define LE_TO_H16(x) (x)
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#define LE_TO_H32(x) (x)
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#define H_TO_LE16(x) (x)
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#define H_TO_LE32(x) (x)
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#define BE_TO_H16(x) SWAP_16(x)
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#define BE_TO_H32(x) SWAP_32(x)
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#define H_TO_BE16(x) SWAP_16(x)
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#define H_TO_BE32(x) SWAP_32(x)
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#else
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#define LE_TO_H16(x) SWAP_16(x)
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#define LE_TO_H32(x) SWAP_32(x)
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#define H_TO_LE16(x) SWAP_16(x)
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#define H_TO_LE32(x) SWAP_32(x)
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#define BE_TO_H16(x) (x)
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#define BE_TO_H32(x) (x)
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#define H_TO_BE16(x) (x)
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#define H_TO_BE32(x) (x)
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#endif
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#define nop \
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asm volatile ("nop")
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/* gcc 3.4 changed the format of the constraints */
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#if (__GNUC__ >= 3) && (__GNUC_MINOR__ > 3) || (__GNUC__ >= 4)
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#define I_CONSTRAINT "I08"
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#else
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#define I_CONSTRAINT "I"
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#endif
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/* Utilize the user break controller to catch invalid memory accesses. */
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int system_memory_guard(int newmode);
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enum {
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MEMGUARD_KEEP = -1, /* don't change the mode; for reading */
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MEMGUARD_NONE = 0, /* catch nothing */
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MEMGUARD_FLASH_WRITES, /* catch writes to area 02 (flash ROM) */
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MEMGUARD_ZERO_AREA, /* catch all accesses to areas 00 and 01 */
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MAXMEMGUARD
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};
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#ifndef SIMULATOR
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#ifdef CPU_COLDFIRE
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#include "system-target.h"
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#endif
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#endif
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#if CONFIG_CPU == SH7034
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#define or_b(mask, address) \
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asm \
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("or.b %0,@(r0,gbr)" \
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: \
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: /* %0 */ I_CONSTRAINT((char)(mask)), \
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/* %1 */ "z"(address-GBR))
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#define and_b(mask, address) \
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asm \
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("and.b %0,@(r0,gbr)" \
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: \
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: /* %0 */ I_CONSTRAINT((char)(mask)), \
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/* %1 */ "z"(address-GBR))
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#define xor_b(mask, address) \
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asm \
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("xor.b %0,@(r0,gbr)" \
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: \
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: /* %0 */ I_CONSTRAINT((char)(mask)), \
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/* %1 */ "z"(address-GBR))
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#endif /* CONFIG_CPU == SH7034 */
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#ifndef SIMULATOR
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/****************************************************************************
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* Interrupt level setting
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* The level is left shifted 4 bits
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****************************************************************************/
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#if CONFIG_CPU == SH7034
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#define HIGHEST_IRQ_LEVEL (15<<4)
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static inline int set_irq_level(int level)
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{
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int i;
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/* Read the old level and set the new one */
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asm volatile ("stc sr, %0" : "=r" (i));
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asm volatile ("ldc %0, sr" : : "r" (level));
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return i;
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}
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static inline unsigned short swap16(unsigned short value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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unsigned short result;
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asm volatile ("swap.b\t%1,%0" : "=r"(result) : "r"(value));
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return result;
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}
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static inline unsigned long SWAW32(unsigned long value)
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/*
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result[31..16] = value[15.. 0];
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result[15.. 0] = value[31..16];
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*/
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{
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unsigned long result;
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asm volatile ("swap.w\t%1,%0" : "=r"(result) : "r"(value));
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return result;
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}
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static inline unsigned long swap32(unsigned long value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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asm volatile ("swap.b\t%0,%0\n"
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"swap.w\t%0,%0\n"
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"swap.b\t%0,%0\n" : "+r"(value));
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return value;
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}
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#define invalidate_icache()
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#elif defined(CPU_ARM)
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/* TODO: Implement set_irq_level and check CPU frequencies */
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#define CPUFREQ_DEFAULT_MULT 8
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#define CPUFREQ_DEFAULT 24000000
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#define CPUFREQ_NORMAL_MULT 10
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#define CPUFREQ_NORMAL 30000000
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#define CPUFREQ_MAX_MULT 25
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#define CPUFREQ_MAX 75000000
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static inline unsigned short swap16(unsigned short value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline unsigned long swap32(unsigned long value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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unsigned int tmp;
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asm volatile (
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"eor %1, %0, %0, ror #16 \n\t"
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"bic %1, %1, #0xff0000 \n\t"
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"mov %0, %0, ror #8 \n\t"
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"eor %0, %0, %1, lsr #8 \n\t"
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: "+r" (value), "=r" (tmp)
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);
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return value;
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}
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#define HIGHEST_IRQ_LEVEL (1)
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static inline int set_irq_level(int level)
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{
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unsigned long cpsr;
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/* Read the old level and set the new one */
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asm volatile ("mrs %0,cpsr" : "=r" (cpsr));
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asm volatile ("msr cpsr_c,%0"
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: : "r" ((cpsr & ~0x80) | (level << 7)));
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return (cpsr >> 7) & 1;
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}
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static inline void enable_fiq(void)
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{
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/* Clear FIQ disable bit */
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asm volatile (
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"mrs r0, cpsr \n"\
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"bic r0, r0, #0x40 \n"\
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"msr cpsr_c, r0 "
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: : : "r0"
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);
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}
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static inline void disable_fiq(void)
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{
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/* Set FIQ disable bit */
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asm volatile (
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"mrs r0, cpsr \n"\
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"orr r0, r0, #0x40 \n"\
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"msr cpsr_c, r0 "
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: : : "r0"
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);
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}
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#define invalidate_icache()
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#if CONFIG_CPU == PNX0101
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typedef void (*interrupt_handler_t)(void);
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void irq_set_int_handler(int n, interrupt_handler_t handler);
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void irq_enable_int(int n);
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#endif
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#endif
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#ifndef CPU_COLDFIRE
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static inline unsigned long swap_odd_even32(unsigned long value)
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{
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/*
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result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
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result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
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*/
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unsigned long t = value & 0xff00ff00;
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return (t >> 8) | ((t ^ value) << 8);
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}
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#endif
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#else /* SIMULATOR */
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static inline unsigned short swap16(unsigned short value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline unsigned long swap32(unsigned long value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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unsigned long hi = swap16(value >> 16);
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unsigned long lo = swap16(value & 0xffff);
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return (lo << 16) | hi;
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}
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static inline unsigned long swap_odd_even32(unsigned long value)
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{
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/*
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result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
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result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
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*/
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unsigned long t = value & 0xff00ff00;
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return (t >> 8) | ((t ^ value) << 8);
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}
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#define invalidate_icache()
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#endif /* !SIMULATOR */
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#endif /* __SYSTEM_H__ */
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