bdf4d3927c
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14764 a1c6a512-1295-4272-9138-f99709370657
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_ARM_H
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#define SYSTEM_ARM_H
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#define nop \
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asm volatile ("nop")
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/* This gets too complicated otherwise with all the ARM variation and would
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have conflicts with another system-target.h elsewhere so include a
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subheader from here. */
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static inline uint16_t swap16(uint16_t value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline uint32_t swap32(uint32_t value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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uint32_t tmp;
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asm volatile (
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"eor %1, %0, %0, ror #16 \n\t"
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"bic %1, %1, #0xff0000 \n\t"
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"mov %0, %0, ror #8 \n\t"
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"eor %0, %0, %1, lsr #8 \n\t"
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: "+r" (value), "=r" (tmp)
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);
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return value;
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}
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static inline uint32_t swap_odd_even32(uint32_t value)
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{
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/*
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result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
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result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
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*/
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uint32_t tmp;
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asm volatile ( /* ABCD */
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"bic %1, %0, #0x00ff00 \n\t" /* AB.D */
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"bic %0, %0, #0xff0000 \n\t" /* A.CD */
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"mov %0, %0, lsr #8 \n\t" /* .A.C */
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"orr %0, %0, %1, lsl #8 \n\t" /* B.D.|.A.C */
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: "+r" (value), "=r" (tmp) /* BADC */
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);
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return value;
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}
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static inline void set_fiq_handler(void(*fiq_handler)(void))
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{
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/* Install the FIQ handler */
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*((unsigned int*)(15*4)) = (unsigned int)fiq_handler;
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}
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static inline void enable_fiq(void)
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{
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/* Clear FIQ disable bit */
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asm volatile (
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"mrs r0, cpsr \n"\
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"bic r0, r0, #0x40 \n"\
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"msr cpsr_c, r0 "
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: : : "r0"
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);
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}
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static inline void disable_fiq(void)
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{
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/* Set FIQ disable bit */
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asm volatile (
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"mrs r0, cpsr \n"\
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"orr r0, r0, #0x40 \n"\
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"msr cpsr_c, r0 "
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: : : "r0"
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);
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}
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/* This one returns the old status */
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#define IRQ_ENABLED 0x00
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#define IRQ_DISABLED 0x80
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#define IRQ_STATUS 0x80
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#define FIQ_ENABLED 0x00
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#define FIQ_DISABLED 0x40
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#define FIQ_STATUS 0x40
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#define IRQ_FIQ_ENABLED 0x00
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#define IRQ_FIQ_DISABLED 0xc0
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#define IRQ_FIQ_STATUS 0xc0
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#define HIGHEST_IRQ_LEVEL IRQ_DISABLED
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#define set_irq_level(status) set_interrupt_status((status), IRQ_STATUS)
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#define set_fiq_status(status) set_interrupt_status((status), FIQ_STATUS)
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static inline int set_interrupt_status(int status, int mask)
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{
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unsigned long cpsr;
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int oldstatus;
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/* Read the old levels and set the new ones */
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asm volatile (
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"mrs %1, cpsr \n"
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"bic %0, %1, %[mask] \n"
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"orr %0, %0, %2 \n"
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"msr cpsr_c, %0 \n"
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: "=&r,r"(cpsr), "=&r,r"(oldstatus)
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: "r,i"(status & mask), [mask]"i,i"(mask)
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);
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return oldstatus;
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}
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#endif /* SYSTEM_ARM_H */
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