2e99b3d931
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19619 a1c6a512-1295-4272-9138-f99709370657
581 lines
19 KiB
C
581 lines
19 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Michael Sevakis
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*
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* Driver for WM8978 audio codec
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "audiohw.h"
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#include "wmcodec.h"
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#include "audio.h"
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//#define LOGF_ENABLE
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#include "logf.h"
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/* TODO: Define/refine an API for special hardware steps outside the
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* main codec driver such as special GPIO handling. */
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/* NOTE: Much of the volume code is very interdependent and calibrated for
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* the Gigabeat S. If you change anything for another device that uses this
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* file it may break things. */
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extern void audiohw_enable_headphone_jack(bool enable);
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const struct sound_settings_info audiohw_settings[] =
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{
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[SOUND_VOLUME] = {"dB", 0, 1, -90, 6, -25},
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[SOUND_BASS] = {"dB", 0, 1, -12, 12, 0},
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[SOUND_TREBLE] = {"dB", 0, 1, -12, 12, 0},
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[SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
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[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
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[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
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#ifdef HAVE_RECORDING
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/* Digital: -119.0dB to +8.0dB in 0.5dB increments
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* Analog: Relegated to volume control
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* Circumstances unfortunately do not allow a great deal of positive
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* gain. */
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[SOUND_LEFT_GAIN] = {"dB", 1, 1,-238, 16, 0},
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[SOUND_RIGHT_GAIN] = {"dB", 1, 1,-238, 16, 0},
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#if 0
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[SOUND_MIC_GAIN] = {"dB", 1, 1,-238, 16, 0},
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#endif
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#endif
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#if 0
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[SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 1},
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[SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
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#endif
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};
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static uint16_t wmc_regs[WMC_NUM_REGISTERS] =
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{
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/* Initialized with post-reset default values - the 2-wire interface
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* cannot be read. Or-in additional bits desired for some registers. */
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[0 ... WMC_NUM_REGISTERS-1] = 0x8000, /* To ID invalids in gaps */
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[WMC_SOFTWARE_RESET] = 0x000,
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[WMC_POWER_MANAGEMENT1] = 0x000,
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[WMC_POWER_MANAGEMENT2] = 0x000,
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[WMC_POWER_MANAGEMENT3] = 0x000,
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[WMC_AUDIO_INTERFACE] = 0x050,
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[WMC_COMPANDING_CTRL] = 0x000,
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[WMC_CLOCK_GEN_CTRL] = 0x140,
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[WMC_ADDITIONAL_CTRL] = 0x000,
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[WMC_GPIO] = 0x000,
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[WMC_JACK_DETECT_CONTROL1] = 0x000,
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[WMC_DAC_CONTROL] = 0x000,
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[WMC_LEFT_DAC_DIGITAL_VOL] = 0x0ff | WMC_VU,
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[WMC_RIGHT_DAC_DIGITAL_VOL] = 0x0ff | WMC_VU,
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[WMC_JACK_DETECT_CONTROL2] = 0x000,
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[WMC_ADC_CONTROL] = 0x100,
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[WMC_LEFT_ADC_DIGITAL_VOL] = 0x0ff | WMC_VU,
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[WMC_RIGHT_ADC_DIGITAL_VOL] = 0x0ff | WMC_VU,
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[WMC_EQ1_LOW_SHELF] = 0x12c,
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[WMC_EQ2_PEAK1] = 0x02c,
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[WMC_EQ3_PEAK2] = 0x02c,
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[WMC_EQ4_PEAK3] = 0x02c,
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[WMC_EQ5_HIGH_SHELF] = 0x02c,
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[WMC_DAC_LIMITER1] = 0x032,
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[WMC_DAC_LIMITER2] = 0x000,
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[WMC_NOTCH_FILTER1] = 0x000,
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[WMC_NOTCH_FILTER2] = 0x000,
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[WMC_NOTCH_FILTER3] = 0x000,
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[WMC_NOTCH_FILTER4] = 0x000,
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[WMC_ALC_CONTROL1] = 0x038,
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[WMC_ALC_CONTROL2] = 0x00b,
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[WMC_ALC_CONTROL3] = 0x032,
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[WMC_NOISE_GATE] = 0x000,
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[WMC_PLL_N] = 0x008,
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[WMC_PLL_K1] = 0x00c,
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[WMC_PLL_K2] = 0x093,
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[WMC_PLL_K3] = 0x0e9,
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[WMC_3D_CONTROL] = 0x000,
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[WMC_BEEP_CONTROL] = 0x000,
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[WMC_INPUT_CTRL] = 0x033,
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[WMC_LEFT_INP_PGA_GAIN_CTRL] = 0x010 | WMC_VU | WMC_ZC,
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[WMC_RIGHT_INP_PGA_GAIN_CTRL] = 0x010 | WMC_VU | WMC_ZC,
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[WMC_LEFT_ADC_BOOST_CTRL] = 0x100,
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[WMC_RIGHT_ADC_BOOST_CTRL] = 0x100,
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[WMC_OUTPUT_CTRL] = 0x002,
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[WMC_LEFT_MIXER_CTRL] = 0x001,
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[WMC_RIGHT_MIXER_CTRL] = 0x001,
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[WMC_LOUT1_HP_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
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[WMC_ROUT1_HP_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
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[WMC_LOUT2_SPK_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
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[WMC_ROUT2_SPK_VOLUME_CTRL] = 0x039 | WMC_VU | WMC_ZC,
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[WMC_OUT3_MIXER_CTRL] = 0x001,
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[WMC_OUT4_MONO_MIXER_CTRL] = 0x001,
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};
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struct
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{
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int vol_l;
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int vol_r;
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bool ahw_mute;
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} wmc_vol =
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{
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0, 0, false
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};
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static void wmc_write(unsigned int reg, unsigned int val)
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{
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if (reg >= WMC_NUM_REGISTERS || (wmc_regs[reg] & 0x8000))
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{
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logf("wm8978 invalid register: %d", reg);
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return;
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}
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wmc_regs[reg] = val & ~0x8000;
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wmcodec_write(reg, val);
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}
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void wmc_set(unsigned int reg, unsigned int bits)
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{
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wmc_write(reg, wmc_regs[reg] | bits);
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}
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void wmc_clear(unsigned int reg, unsigned int bits)
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{
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wmc_write(reg, wmc_regs[reg] & ~bits);
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}
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static void wmc_write_masked(unsigned int reg, unsigned int bits,
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unsigned int mask)
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{
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wmc_write(reg, (wmc_regs[reg] & ~mask) | (bits & mask));
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}
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/* convert tenth of dB volume (-890..60) to master volume register value
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* (000000...111111) */
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int tenthdb2master(int db)
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{
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/* -90dB to +6dB 1dB steps (96 levels) 7bits */
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/* 1100000 == +6dB (0x60,96) */
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/* 1101010 == 0dB (0x5a,90) */
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/* 1000001 == -57dB (0x21,33,DAC) */
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/* 0000001 == -89dB (0x01,01) */
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/* 0000000 == -90dB (0x00,00,Mute) */
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if (db <= VOLUME_MIN)
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{
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return 0x0;
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}
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else
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{
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return (db - VOLUME_MIN) / 10;
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}
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}
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int sound_val2phys(int setting, int value)
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{
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int result;
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switch (setting)
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{
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#ifdef HAVE_RECORDING
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case SOUND_LEFT_GAIN:
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case SOUND_RIGHT_GAIN:
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case SOUND_MIC_GAIN:
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result = value * 5;
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break;
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#endif
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default:
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result = value;
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}
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return result;
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}
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void audiohw_preinit(void)
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{
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/* 1. Turn on external power supplies. Wait for supply voltage to settle. */
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/* Step 1 should be completed already. Reset and return all registers to
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* defaults */
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wmcodec_write(WMC_SOFTWARE_RESET, 0xff);
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sleep(HZ/10);
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/* 2. Mute all analogue outputs */
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wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
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wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
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wmc_set(WMC_LOUT2_SPK_VOLUME_CTRL, WMC_MUTE);
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wmc_set(WMC_ROUT2_SPK_VOLUME_CTRL, WMC_MUTE);
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wmc_set(WMC_OUT3_MIXER_CTRL, WMC_MUTE);
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wmc_set(WMC_OUT4_MONO_MIXER_CTRL, WMC_MUTE);
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/* 3. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3. */
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wmc_write(WMC_POWER_MANAGEMENT3,
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WMC_RMIXEN | WMC_LMIXEN | WMC_DACENR | WMC_DACENL);
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/* 4. Set BUFIOEN = 1 and VMIDSEL[1:0] to required value in register
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* R1. Wait for VMID supply to settle */
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wmc_write(WMC_POWER_MANAGEMENT1, WMC_BUFIOEN | WMC_VMIDSEL_300K);
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sleep(HZ/10);
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/* 5. Set BIASEN = 1 in register R1. */
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wmc_set(WMC_POWER_MANAGEMENT1, WMC_BIASEN);
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}
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void audiohw_postinit(void)
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{
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sleep(HZ);
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/* 6. Set L/ROUTEN = 1 in register R2. */
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wmc_write(WMC_POWER_MANAGEMENT2, WMC_LOUT1EN | WMC_ROUT1EN);
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/* 7. Enable other mixers as required */
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/* 8. Enable other outputs as required */
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/* 9. Set remaining registers */
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wmc_write(WMC_AUDIO_INTERFACE, WMC_WL_16 | WMC_FMT_I2S);
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wmc_write(WMC_DAC_CONTROL, WMC_DACOSR_128 | WMC_AMUTE);
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/* No ADC, no HP filter, no popping */
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wmc_clear(WMC_ADC_CONTROL, WMC_HPFEN);
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wmc_clear(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
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wmc_clear(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
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/* Specific to HW clocking */
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wmc_write_masked(WMC_CLOCK_GEN_CTRL, WMC_BCLKDIV_4 | WMC_MS,
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WMC_BCLKDIV | WMC_MS | WMC_CLKSEL);
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audiohw_set_frequency(HW_FREQ_DEFAULT);
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audiohw_enable_headphone_jack(true);
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}
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static void get_headphone_levels(int val, int *dac_p, int *hp_p,
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int *mix_p, int *boost_p)
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{
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int dac, hp, mix, boost;
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if (val >= 33)
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{
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dac = 255;
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hp = val - 33;
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mix = 7;
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boost = 5;
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}
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else if (val >= 21)
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{
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dac = 189 + val / 3 * 6;
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hp = val % 3;
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mix = 7;
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boost = (val - 18) / 3;
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}
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else
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{
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dac = 189 + val / 3 * 6;
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hp = val % 3;
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mix = val / 3;
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boost = 1;
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}
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*dac_p = dac;
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*hp_p = hp;
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*mix_p = mix;
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*boost_p = boost;
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}
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void audiohw_set_headphone_vol(int vol_l, int vol_r)
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{
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int prev_l = wmc_vol.vol_l;
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int prev_r = wmc_vol.vol_r;
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int dac_l, dac_r, hp_l, hp_r;
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int mix_l, mix_r, boost_l, boost_r;
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wmc_vol.vol_l = vol_l;
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wmc_vol.vol_r = vol_r;
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/* Mixers are synced to provide full volume range on both the analogue
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* and digital pathways */
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get_headphone_levels(vol_l, &dac_l, &hp_l, &mix_l, &boost_l);
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get_headphone_levels(vol_r, &dac_r, &hp_r, &mix_r, &boost_r);
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wmc_write_masked(WMC_LEFT_MIXER_CTRL, WMC_BYPLMIXVOLw(mix_l),
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WMC_BYPLMIXVOL);
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wmc_write_masked(WMC_LEFT_ADC_BOOST_CTRL,
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WMC_L2_2BOOSTVOLw(boost_l), WMC_L2_2BOOSTVOL);
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wmc_write_masked(WMC_LEFT_DAC_DIGITAL_VOL, dac_l, WMC_DVOL);
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wmc_write_masked(WMC_LOUT1_HP_VOLUME_CTRL, hp_l, WMC_AVOL);
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wmc_write_masked(WMC_RIGHT_MIXER_CTRL, WMC_BYPRMIXVOLw(mix_r),
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WMC_BYPRMIXVOL);
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wmc_write_masked(WMC_RIGHT_ADC_BOOST_CTRL,
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WMC_R2_2BOOSTVOLw(boost_r), WMC_R2_2BOOSTVOL);
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wmc_write_masked(WMC_RIGHT_DAC_DIGITAL_VOL, dac_r, WMC_DVOL);
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wmc_write_masked(WMC_ROUT1_HP_VOLUME_CTRL, hp_r, WMC_AVOL);
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if (vol_l > 0)
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{
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/* Not muted and going up from mute level? */
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if (prev_l <= 0 && !wmc_vol.ahw_mute)
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wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
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}
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else
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{
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/* Going to mute level? */
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if (prev_l > 0)
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wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
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}
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if (vol_r > 0)
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{
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/* Not muted and going up from mute level? */
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if (prev_r <= 0 && !wmc_vol.ahw_mute)
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wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
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}
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else
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{
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/* Going to mute level? */
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if (prev_r > 0)
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wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
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}
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}
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void audiohw_close(void)
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{
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/* 1. Mute all analogue outputs */
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audiohw_mute(true);
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audiohw_enable_headphone_jack(false);
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/* 2. Disable power management register 1. R1 = 00 */
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wmc_write(WMC_POWER_MANAGEMENT1, 0x000);
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/* 3. Disable power management register 2. R2 = 00 */
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wmc_write(WMC_POWER_MANAGEMENT2, 0x000);
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/* 4. Disable power management register 3. R3 = 00 */
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wmc_write(WMC_POWER_MANAGEMENT3, 0x000);
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/* 5. Remove external power supplies. */
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}
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void audiohw_mute(bool mute)
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{
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wmc_vol.ahw_mute = mute;
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/* No DAC mute here, please - take care of each enabled output. */
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if (mute)
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{
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wmc_set(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
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wmc_set(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
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}
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else
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{
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/* Unmute outputs not at mute level */
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if (wmc_vol.vol_l > 0)
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wmc_clear(WMC_LOUT1_HP_VOLUME_CTRL, WMC_MUTE);
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if (wmc_vol.vol_r > 0)
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wmc_clear(WMC_ROUT1_HP_VOLUME_CTRL, WMC_MUTE);
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}
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}
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void audiohw_set_frequency(int fsel)
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{
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/* For 16.9344MHz MCLK, codec as master. */
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static const struct
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{
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uint32_t plln : 8;
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uint32_t pllk1 : 6;
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uint32_t pllk2 : 9;
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uint32_t pllk3 : 9;
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unsigned char mclkdiv;
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unsigned char filter;
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} srctrl_table[HW_NUM_FREQ] =
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{
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[HW_FREQ_8] = /* PLL = 65.536MHz */
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{
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.plln = WMC_PLLNw(7) | WMC_PLL_PRESCALE,
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.pllk1 = WMC_PLLK_23_18w(12414886ul >> 18),
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.pllk2 = WMC_PLLK_17_9w(12414886ul >> 9),
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.pllk3 = WMC_PLLK_8_0w(12414886ul >> 0),
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.mclkdiv = WMC_MCLKDIV_8, /* 2.0480 MHz */
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.filter = WMC_SR_8KHZ,
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},
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[HW_FREQ_11] = /* PLL = off */
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{
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.mclkdiv = WMC_MCLKDIV_6, /* 2.8224 MHz */
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.filter = WMC_SR_12KHZ,
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},
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[HW_FREQ_12] = /* PLL = 73.728 MHz */
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{
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.plln = WMC_PLLNw(8) | WMC_PLL_PRESCALE,
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.pllk1 = WMC_PLLK_23_18w(11869595ul >> 18),
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.pllk2 = WMC_PLLK_17_9w(11869595ul >> 9),
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.pllk3 = WMC_PLLK_8_0w(11869595ul >> 0),
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.mclkdiv = WMC_MCLKDIV_6, /* 3.0720 MHz */
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.filter = WMC_SR_12KHZ,
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},
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[HW_FREQ_16] = /* PLL = 65.536MHz */
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{
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.plln = WMC_PLLNw(7) | WMC_PLL_PRESCALE,
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.pllk1 = WMC_PLLK_23_18w(12414886ul >> 18),
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.pllk2 = WMC_PLLK_17_9w(12414886ul >> 9),
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.pllk3 = WMC_PLLK_8_0w(12414886ul >> 0),
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.mclkdiv = WMC_MCLKDIV_4, /* 4.0960 MHz */
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.filter = WMC_SR_16KHZ,
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},
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|
[HW_FREQ_22] = /* PLL = off */
|
|
{
|
|
.mclkdiv = WMC_MCLKDIV_3, /* 5.6448 MHz */
|
|
.filter = WMC_SR_24KHZ,
|
|
},
|
|
[HW_FREQ_24] = /* PLL = 73.728 MHz */
|
|
{
|
|
.plln = WMC_PLLNw(8) | WMC_PLL_PRESCALE,
|
|
.pllk1 = WMC_PLLK_23_18w(11869595ul >> 18),
|
|
.pllk2 = WMC_PLLK_17_9w(11869595ul >> 9),
|
|
.pllk3 = WMC_PLLK_8_0w(11869595ul >> 0),
|
|
.mclkdiv = WMC_MCLKDIV_3, /* 6.1440 MHz */
|
|
.filter = WMC_SR_24KHZ,
|
|
},
|
|
[HW_FREQ_32] = /* PLL = 65.536MHz */
|
|
{
|
|
.plln = WMC_PLLNw(7) | WMC_PLL_PRESCALE,
|
|
.pllk1 = WMC_PLLK_23_18w(12414886ul >> 18),
|
|
.pllk2 = WMC_PLLK_17_9w(12414886ul >> 9),
|
|
.pllk3 = WMC_PLLK_8_0w(12414886ul >> 0),
|
|
.mclkdiv = WMC_MCLKDIV_2, /* 8.1920 MHz */
|
|
.filter = WMC_SR_32KHZ,
|
|
},
|
|
[HW_FREQ_44] = /* PLL = off */
|
|
{
|
|
.mclkdiv = WMC_MCLKDIV_1_5, /* 11.2896 MHz */
|
|
.filter = WMC_SR_48KHZ,
|
|
},
|
|
[HW_FREQ_48] = /* PLL = 73.728 MHz */
|
|
{
|
|
.plln = WMC_PLLNw(8) | WMC_PLL_PRESCALE,
|
|
.pllk1 = WMC_PLLK_23_18w(11869595ul >> 18),
|
|
.pllk2 = WMC_PLLK_17_9w(11869595ul >> 9),
|
|
.pllk3 = WMC_PLLK_8_0w(11869595ul >> 0),
|
|
.mclkdiv = WMC_MCLKDIV_1_5, /* 12.2880 MHz */
|
|
.filter = WMC_SR_48KHZ,
|
|
},
|
|
};
|
|
|
|
unsigned int plln;
|
|
unsigned int mclkdiv;
|
|
|
|
if ((unsigned)fsel >= HW_NUM_FREQ)
|
|
fsel = HW_FREQ_DEFAULT;
|
|
|
|
/* Setup filters. */
|
|
wmc_write(WMC_ADDITIONAL_CTRL, srctrl_table[fsel].filter);
|
|
|
|
plln = srctrl_table[fsel].plln;
|
|
mclkdiv = srctrl_table[fsel].mclkdiv;
|
|
|
|
if (plln != 0)
|
|
{
|
|
/* Using PLL to generate SYSCLK */
|
|
|
|
/* Program PLL. */
|
|
wmc_write(WMC_PLL_N, plln);
|
|
wmc_write(WMC_PLL_K1, srctrl_table[fsel].pllk1);
|
|
wmc_write(WMC_PLL_K2, srctrl_table[fsel].pllk2);
|
|
wmc_write(WMC_PLL_K3, srctrl_table[fsel].pllk3);
|
|
|
|
/* Turn on PLL. */
|
|
wmc_set(WMC_POWER_MANAGEMENT1, WMC_PLLEN);
|
|
|
|
/* Switch to PLL and set divider. */
|
|
wmc_write_masked(WMC_CLOCK_GEN_CTRL, mclkdiv | WMC_CLKSEL,
|
|
WMC_MCLKDIV | WMC_CLKSEL);
|
|
}
|
|
else
|
|
{
|
|
/* Switch away from PLL and set MCLKDIV. */
|
|
wmc_write_masked(WMC_CLOCK_GEN_CTRL, mclkdiv,
|
|
WMC_MCLKDIV | WMC_CLKSEL);
|
|
|
|
/* Turn off PLL. */
|
|
wmc_clear(WMC_POWER_MANAGEMENT1, WMC_PLLEN);
|
|
}
|
|
}
|
|
|
|
#ifdef HAVE_RECORDING
|
|
void audiohw_set_recsrc(int source, bool recording)
|
|
{
|
|
switch (source)
|
|
{
|
|
case AUDIO_SRC_PLAYBACK:
|
|
/* Disable all audio paths but DAC */
|
|
/* Disable ADCs */
|
|
wmc_clear(WMC_ADC_CONTROL, WMC_HPFEN);
|
|
wmc_clear(WMC_POWER_MANAGEMENT2, WMC_ADCENL | WMC_ADCENR);
|
|
/* Disable bypass */
|
|
wmc_clear(WMC_LEFT_MIXER_CTRL, WMC_BYPL2LMIX);
|
|
wmc_clear(WMC_RIGHT_MIXER_CTRL, WMC_BYPR2RMIX);
|
|
/* Disable IP BOOSTMIX and PGA */
|
|
wmc_clear(WMC_POWER_MANAGEMENT2, WMC_INPPGAENL | WMC_INPPGAENR |
|
|
WMC_BOOSTENL | WMC_BOOSTENR);
|
|
wmc_clear(WMC_INPUT_CTRL, WMC_L2_2INPPGA | WMC_R2_2INPPGA);
|
|
wmc_clear(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
|
|
wmc_clear(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
|
|
break;
|
|
|
|
case AUDIO_SRC_FMRADIO:
|
|
if (recording)
|
|
{
|
|
/* Disable bypass */
|
|
wmc_clear(WMC_LEFT_MIXER_CTRL, WMC_BYPL2LMIX);
|
|
wmc_clear(WMC_RIGHT_MIXER_CTRL, WMC_BYPR2RMIX);
|
|
/* Enable ADCs, IP BOOSTMIX and PGA, route L/R2 through PGA */
|
|
wmc_set(WMC_POWER_MANAGEMENT2, WMC_ADCENL | WMC_ADCENR |
|
|
WMC_BOOSTENL | WMC_BOOSTENR | WMC_INPPGAENL |
|
|
WMC_INPPGAENR);
|
|
wmc_set(WMC_ADC_CONTROL, WMC_ADCOSR | WMC_HPFEN);
|
|
/* PGA at 0dB with +20dB boost */
|
|
wmc_write_masked(WMC_LEFT_INP_PGA_GAIN_CTRL, 0x10, WMC_AVOL);
|
|
wmc_write_masked(WMC_RIGHT_INP_PGA_GAIN_CTRL, 0x10, WMC_AVOL);
|
|
wmc_set(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
|
|
wmc_set(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
|
|
/* Connect L/R2 inputs to PGA */
|
|
wmc_set(WMC_INPUT_CTRL, WMC_L2_2INPPGA | WMC_R2_2INPPGA);
|
|
}
|
|
else
|
|
{
|
|
/* Disable PGA and ADC, enable IP BOOSTMIX, route L/R2 directly to
|
|
* IP BOOSTMIX */
|
|
wmc_clear(WMC_ADC_CONTROL, WMC_HPFEN);
|
|
wmc_write_masked(WMC_POWER_MANAGEMENT2, WMC_BOOSTENL | WMC_BOOSTENR,
|
|
WMC_BOOSTENL | WMC_BOOSTENR | WMC_INPPGAENL |
|
|
WMC_INPPGAENR | WMC_ADCENL | WMC_ADCENR);
|
|
wmc_clear(WMC_INPUT_CTRL, WMC_L2_2INPPGA | WMC_R2_2INPPGA);
|
|
wmc_clear(WMC_LEFT_ADC_BOOST_CTRL, WMC_PGABOOSTL);
|
|
wmc_clear(WMC_RIGHT_ADC_BOOST_CTRL, WMC_PGABOOSTR);
|
|
/* Enable bypass to L/R mixers */
|
|
wmc_set(WMC_LEFT_MIXER_CTRL, WMC_BYPL2LMIX);
|
|
wmc_set(WMC_RIGHT_MIXER_CTRL, WMC_BYPR2RMIX);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
void audiohw_set_recvol(int left, int right, int type)
|
|
{
|
|
switch (type)
|
|
{
|
|
case AUDIO_GAIN_LINEIN:
|
|
wmc_write_masked(WMC_LEFT_ADC_DIGITAL_VOL, left + 239, WMC_DVOL);
|
|
wmc_write_masked(WMC_RIGHT_ADC_DIGITAL_VOL, right + 239, WMC_DVOL);
|
|
return;
|
|
}
|
|
}
|
|
#endif /* HAVE_RECORDING */
|