7fa6bc7750
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17173 a1c6a512-1295-4272-9138-f99709370657
453 lines
15 KiB
C
453 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "thread.h"
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#include "i2s.h"
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#include "i2c-pp.h"
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#include "as3514.h"
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#ifdef HAVE_USBSTACK
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#include "usb_drv.h"
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#endif
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#ifndef BOOTLOADER
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extern void TIMER1(void);
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extern void TIMER2(void);
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extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */
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extern void ipod_4g_button_int(void); /* iPod 4th gen and higher only */
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extern void microsd_int(void); /* Sansa E200 and C200 */
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#ifdef SANSA_E200
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extern void button_int(void);
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extern void clickwheel_int(void);
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#endif
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#ifdef MROBE_100
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extern void button_int(void);
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#endif
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK) {
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TIMER1();
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} else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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#if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */
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else if (CPU_HI_INT_STAT & GPIO0_MASK)
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ipod_mini_button_int();
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#elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */
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else if (CPU_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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#elif defined(SANSA_E200)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOA_INT_STAT & 0x80)
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microsd_int();
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}
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else if (CPU_HI_INT_STAT & GPIO1_MASK) {
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if (GPIOF_INT_STAT & 0xff)
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button_int();
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if (GPIOH_INT_STAT & 0xc0)
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clickwheel_int();
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}
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#elif defined(SANSA_C200)
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else if (CPU_HI_INT_STAT & GPIO2_MASK) {
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if (GPIOL_INT_STAT & 0x08)
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microsd_int();
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}
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#elif defined(MROBE_100)
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else if (CPU_HI_INT_STAT & GPIO0_MASK) {
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if (GPIOD_INT_STAT & 0x2)
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button_int();
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}
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#endif
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#ifdef HAVE_USBSTACK
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else if (CPU_INT_STAT & USB_MASK) {
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usb_drv_int();
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}
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#endif
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} else {
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if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#endif /* BOOTLOADER */
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/* TODO: The following function has been lifted straight from IPL, and
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hence has a lot of numeric addresses used straight. I'd like to use
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#defines for these, but don't know what most of them are for or even what
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they should be named. Because of this I also have no way of knowing how
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to extend the funtions to do alternate cache configurations. */
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#ifndef BOOTLOADER
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void flush_icache(void) ICODE_ATTR;
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void flush_icache(void)
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{
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if (CACHE_CTL & CACHE_CTL_ENABLE)
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{
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CACHE_OPERATION |= CACHE_OP_FLUSH;
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while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
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}
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}
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void invalidate_icache(void) ICODE_ATTR;
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void invalidate_icache(void)
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{
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if (CACHE_CTL & CACHE_CTL_ENABLE)
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{
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CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
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while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
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nop; nop; nop; nop;
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}
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}
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static void init_cache(void)
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{
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/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
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/* cache init mode */
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CACHE_CTL |= CACHE_CTL_INIT;
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/* what's this do? */
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CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
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/* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
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* yes: 0x00000000 - 0x03ffffff
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* no: 0x04000000 - 0x1fffffff
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* yes: 0x20000000 - 0x23ffffff
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* no: 0x24000000 - 0x3fffffff
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*/
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CACHE_MASK = 0x00001c00;
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CACHE_OPERATION = 0xfc0;
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/* enable cache */
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CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
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nop; nop; nop; nop;
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}
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#endif /* !BOOTLOADER */
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/* We need this for Sansas since we boost the cpu in their bootloader */
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#if !defined(BOOTLOADER) || defined(SANSA_E200) || defined(SANSA_C200)
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void scale_suspend_core(bool suspend) ICODE_ATTR;
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void scale_suspend_core(bool suspend)
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{
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unsigned int core = CURRENT_CORE;
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IF_COP( unsigned int othercore = 1 - core; )
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static int oldstatus IBSS_ATTR;
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if (suspend)
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{
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oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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IF_COP( PROC_CTL(othercore) = 0x40000000; nop; )
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PROC_CTL(core) = 0x48000003; nop;
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}
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else
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{
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PROC_CTL(core) = 0x4800001f; nop;
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IF_COP( PROC_CTL(othercore) = 0x00000000; nop; )
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restore_interrupt(oldstatus);
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}
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency) ICODE_ATTR;
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void set_cpu_frequency(long frequency)
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#else
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static void pp_set_cpu_frequency(long frequency)
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#endif
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{
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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spinlock_lock(&boostctrl_spin);
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#endif
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switch (frequency)
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{
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/* Note1: The PP5022 PLL must be run at >= 96MHz
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* Bits 20..21 select the post divider (1/2/4/8).
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* PP5026 is similar to PP5022 except it doesn't
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* have this limitation (and the post divider?)
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* Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz,
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* 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL.
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* SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19
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* FAST = PLL / (DIV_FAST + 1), DIV = Bits 20-23 */
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case CPUFREQ_SLEEP:
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cpu_frequency = CPUFREQ_SLEEP;
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PLL_CONTROL |= 0x0c000000;
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */
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scale_suspend_core(false);
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
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break;
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case CPUFREQ_MAX:
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cpu_frequency = CPUFREQ_MAX;
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DEV_INIT2 |= INIT_PLL; /* enable PLL power */
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PLL_CONTROL |= 0x88000000; /* enable PLL */
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
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DEV_TIMING1 = 0x00000303;
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scale_suspend_core(false);
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#if defined(IPOD_MINI2G)
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MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
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#elif defined(IPOD_NANO)
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IDE0_CFG |= 0x10000000; /* set ">65MHz" bit */
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#endif
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */
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PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */
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PLL_CONTROL = 0x8a020a03; /* repeat setup */
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udelay(500); /* wait for relock */
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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PLL_CONTROL = 0x8a121403; /* 80 MHz = (20/3 * 24MHz) / 2 */
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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#endif
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scale_suspend_core(true);
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DEV_TIMING1 = 0x00000808;
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CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
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scale_suspend_core(false);
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break;
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#if 0 /******** CPUFREQ_NORMAL = 24MHz without PLL ********/
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case CPUFREQ_NORMAL:
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cpu_frequency = CPUFREQ_NORMAL;
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PLL_CONTROL |= 0x08000000;
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
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DEV_TIMING1 = 0x00000303;
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#if defined(IPOD_MINI2G)
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MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
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#elif defined(IPOD_NANO)
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IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */
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#endif
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scale_suspend_core(false);
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
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break;
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#else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/
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case CPUFREQ_NORMAL:
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cpu_frequency = CPUFREQ_NORMAL;
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DEV_INIT2 |= INIT_PLL; /* enable PLL power */
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PLL_CONTROL |= 0x88000000; /* enable PLL */
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
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DEV_TIMING1 = 0x00000303;
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scale_suspend_core(false);
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#if defined(IPOD_MINI2G)
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MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
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#elif defined(IPOD_NANO)
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IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */
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#endif
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020504; /* 30 MHz = 5/4 * 24MHz */
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udelay(500); /* wait for relock */
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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PLL_CONTROL = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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#endif
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scale_suspend_core(true);
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DEV_TIMING1 = 0x00000303;
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CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
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scale_suspend_core(false);
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break;
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#endif /******** CPUFREQ_NORMAL end ********/
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default:
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cpu_frequency = CPUFREQ_DEFAULT;
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PLL_CONTROL |= 0x08000000;
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scale_suspend_core(true);
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CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
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DEV_TIMING1 = 0x00000303;
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#if defined(IPOD_MINI2G)
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MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
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#elif defined(IPOD_NANO)
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IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */
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#endif
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scale_suspend_core(false);
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
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break;
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}
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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spinlock_unlock(&boostctrl_spin);
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#endif
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}
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#endif /* !BOOTLOADER || SANSA_E200 || SANSA_C200 */
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void system_init(void)
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{
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#ifndef BOOTLOADER
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if (CURRENT_CORE == CPU)
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{
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#if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR)
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/* set minimum startup configuration */
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DEV_EN = 0xc2000124;
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DEV_EN2 = 0x00002000;
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CACHE_PRIORITY = 0x0000003f;
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GPO32_VAL = 0x20000000;
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DEV_INIT1 = 0xdc000000;
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DEV_INIT2 = 0x40000000;
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/* reset all allowed devices */
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DEV_RS = 0x3ffffef8;
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DEV_RS2 = 0xffffdfff;
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DEV_RS = 0x00000000;
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DEV_RS2 = 0x00000000;
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#elif defined (IPOD_VIDEO)
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/* set minimum startup configuration */
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DEV_EN = 0xc2000124;
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DEV_EN2 = 0x00000000;
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CACHE_PRIORITY = 0x0000003f;
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GPO32_VAL = 0x00004000;
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DEV_INIT1 = 0x00000000;
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DEV_INIT2 = 0x40000000;
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/* reset all allowed devices */
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DEV_RS = 0x3ffffef8;
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DEV_RS2 = 0xffffffff;
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DEV_RS = 0x00000000;
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DEV_RS2 = 0x00000000;
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#elif defined (IPOD_NANO)
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/* set minimum startup configuration */
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DEV_EN = 0xc2000124;
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DEV_EN2 = 0x00002000;
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CACHE_PRIORITY = 0x0000003f;
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GPO32_VAL = 0x50000000;
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DEV_INIT1 = 0xa8000000;
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DEV_INIT2 = 0x40000000;
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/* reset all allowed devices */
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DEV_RS = 0x3ffffef8;
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DEV_RS2 = 0xffffdfff;
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DEV_RS = 0x00000000;
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DEV_RS2 = 0x00000000;
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#elif defined(SANSA_C200) || defined (SANSA_E200)
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/* set minimum startup configuration */
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DEV_EN = 0xc4000124;
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DEV_EN2 = 0x00000000;
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CACHE_PRIORITY = 0x0000003f;
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GPO32_VAL = 0x10000000;
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DEV_INIT1 = 0x54000000;
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DEV_INIT2 = 0x40000000;
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/* reset all allowed devices */
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DEV_RS = 0x3bfffef8;
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DEV_RS2 = 0xffffffff;
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DEV_RS = 0x00000000;
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DEV_RS2 = 0x00000000;
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#elif defined(IPOD_4G)
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/* set minimum startup configuration */
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DEV_EN = 0xc2020124;
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DEV_EN2 = 0x00000000;
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CACHE_PRIORITY = 0x0000003f;
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GPO32_VAL = 0x02000000;
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DEV_INIT1 = 0x00000000;
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DEV_INIT2 = 0x40000000;
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/* reset all allowed devices */
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DEV_RS = 0x3ffdfef8;
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DEV_RS2 = 0xffffffff;
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DEV_RS = 0x00000000;
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DEV_RS2 = 0x00000000;
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#elif defined (IPOD_MINI)
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/* to be done */
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#elif defined (IPOD_MINI2G)
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/* to be done */
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#elif defined (MROBE_100)
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/* to be done */
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#elif defined (ELIO_TPJ1022)
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/* to be done */
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#endif
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#if !defined(SANSA_E200) && !defined(SANSA_C200)
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/* Remap the flash ROM on CPU, keep hidden from COP:
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* 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */
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MMAP1_LOGICAL = 0x20003c00;
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MMAP1_PHYSICAL = 0x00003084 |
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MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK |
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MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK;
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#endif
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/* disable all irqs */
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COP_HI_INT_CLR = -1;
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CPU_HI_INT_CLR = -1;
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HI_INT_FORCED_CLR = -1;
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COP_INT_CLR = -1;
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CPU_INT_CLR = -1;
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INT_FORCED_CLR = -1;
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GPIOA_INT_EN = 0;
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GPIOB_INT_EN = 0;
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GPIOC_INT_EN = 0;
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GPIOD_INT_EN = 0;
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GPIOE_INT_EN = 0;
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GPIOF_INT_EN = 0;
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GPIOG_INT_EN = 0;
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GPIOH_INT_EN = 0;
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GPIOI_INT_EN = 0;
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GPIOJ_INT_EN = 0;
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GPIOK_INT_EN = 0;
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GPIOL_INT_EN = 0;
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#if defined(SANSA_E200) || defined(SANSA_C200)
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/* outl(0x00000000, 0x6000b000); */
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outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
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#endif
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#if NUM_CORES > 1
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cpu_boost_init();
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#endif
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#else
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pp_set_cpu_frequency(CPUFREQ_MAX);
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#endif
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}
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init_cache();
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#else /* BOOTLOADER */
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if (CURRENT_CORE == CPU)
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{
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#if defined(SANSA_C200) || defined (SANSA_E200)
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pp_set_cpu_frequency(CPUFREQ_MAX);
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#endif
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}
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#endif /* BOOTLOADER */
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}
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void system_reboot(void)
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{
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/* Reboot */
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#if defined(SANSA_E200) || defined(SANSA_C200)
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CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
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/* Magic used by the c200 OF: 0x23066000
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Magic used by the c200 BL: 0x23066b7b
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In both cases, the OF executes these 2 commands from iram. */
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STRAP_OPT_A = 0x23066b7b;
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DEV_RS = DEV_SYSTEM;
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#else
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DEV_RS |= DEV_SYSTEM;
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#endif
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/* wait until reboot kicks in */
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while (1);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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