29b136b82d
* Get USB working (it isn't good at writing support though) * Clean up NAND & SD a bit * Other comments/fixes Ingenic Jz4740/MIPS: * Split MMU from system git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19815 a1c6a512-1295-4272-9138-f99709370657
125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "mips.h"
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#include "mipsregs.h"
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#include "system.h"
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#include "mmu-mips.h"
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#define BARRIER \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" .set reorder \n");
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#define DEFAULT_PAGE_SHIFT PL_4K
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#define DEFAULT_PAGE_MASK PM_4K
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#define UNIQUE_ENTRYHI(idx, ps) (A_K0BASE + ((idx) << (ps + 1)))
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#define ASID_MASK M_EntryHiASID
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#define VPN2_SHIFT S_EntryHiVPN2
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#define PFN_SHIFT S_EntryLoPFN
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#define PFN_MASK 0xffffff
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static void local_flush_tlb_all(void)
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{
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unsigned long old_ctx;
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int entry;
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unsigned int old_irq = disable_irq_save();
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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BARRIER;
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/* Blast 'em all away. */
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for(entry = 0; entry < 32; entry++)
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{
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry, DEFAULT_PAGE_SHIFT));
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write_c0_index(entry);
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BARRIER;
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tlb_write_indexed();
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}
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BARRIER;
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write_c0_entryhi(old_ctx);
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restore_irq(old_irq);
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}
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static void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask)
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{
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unsigned long wired;
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unsigned long old_pagemask;
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unsigned long old_ctx;
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unsigned int old_irq = disable_irq_save();
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old_ctx = read_c0_entryhi() & ASID_MASK;
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old_pagemask = read_c0_pagemask();
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wired = read_c0_wired();
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write_c0_wired(wired + 1);
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write_c0_index(wired);
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BARRIER;
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write_c0_pagemask(pagemask);
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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write_c0_entrylo1(entrylo1);
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BARRIER;
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tlb_write_indexed();
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BARRIER;
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write_c0_entryhi(old_ctx);
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BARRIER;
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write_c0_pagemask(old_pagemask);
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local_flush_tlb_all();
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restore_irq(old_irq);
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}
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void map_address(unsigned long virtual, unsigned long physical, unsigned long length)
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{
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unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT;
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unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT;
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unsigned long entryhi = virtual & ~VPN2_SHIFT;
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entry0 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) );
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entry1 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) );
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add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK);
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}
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void tlb_init(void)
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{
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write_c0_pagemask(DEFAULT_PAGE_MASK);
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write_c0_wired(0);
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write_c0_framemask(0);
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local_flush_tlb_all();
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/*
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map_address(0x80000000, 0x80000000, 0x4000);
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map_address(0x80004000, 0x80004000, MEM * 0x100000);
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*/
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}
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